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| skyworks solutions, inc., pr oprietary and confidential 1 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 data sheet cx74063-3x: rf transceiver with power ramping controller and integrated crystal oscillator with 13 mhz output for multi-band gsm, gprs, and edge applications applications ? gsm850, egsm900, dcs1800, and pcs1900 handsets ? gprs handsets and modules ? edge downlink support features ? direct down-conversion receiver eliminates the external image reject/if filters ? three separate lnas with single-ended inputs ? rf gain range: gsm = 20 db, dcs = 22 db, pcs = 20 db. baseband gain range = 100 db ? gain selectable in 2 db steps ? integrated receive baseband filters with tunable bandwidth ? integrated dc offset correction sequencer ? reduced filtering requirements with translational loop transmit architecture ? integrated transmit vcos ? wide rf range for quad band operation ? integrated pac loop ? single integrated, fully programmable fractional-n synthesizer suitable for multi-slot gprs operation ? fully integrated wideband ultra high frequency (uhf) vco ? integrated crystal oscillator ? separate enable lines for power management transmit, receive, and synthesizer modes ? supply voltage down to 2.6 v ? band select and front-end enable states may be exercised on output pins to control external circuitry. ? low external component count ? optional bypass of baseband filtering for use with high dynamic range analog to digital converters (adcs) for current savings ? interfaces to low dynamic range adc ? meets am suppression requirements without baseband interaction. ? 56-pin rflga 8x8 mm package (low temperature option, cx74063-34; high temperature option, CX74063-35 and cx74063-36) ? low power standby mode description the cx74063-3x transceiver (including C34, -35, and C36 package options) is a highly integrated device for multi-band global system for mobile communications? (gsm?) or general packet radio service (gprs) applications. the device requires a minimal number of external components to complete a gsm radio subsystem. the cx74063-3x supports gsm850, egsm900, dcs1800, a nd pcs1900 applications. the receiver also supports downlink enhanced data-rate gsm evolution (edge). the receive path implements a direct down-conversion architecture that eliminates the need for intermediate frequency (if) components. the cx74063-3x receiver consists of three integrated low noise amplifiers (lnas), a quadrature demodulator, tunable receiver baseband filters, and a dc- offset correction sequencer. in the transmit path, the device consists of an in-phase and quadrature (i/q) modulator within a frequency translation loop designed to perform frequency up-conversion with high output spectral purity. this loop also contains a phase-frequency detector, charge pump, mixer, programmable dividers, and high power transmit voltage controlled oscillators (vcos) with no external tank required. with the integrated gain controller (and an integrator ), the device realizes the power amplifier control (pac) functionality when combined with a coupler, a radio frequency (rf) detector and a power amplifier (pa). the cx74063-3x also features an integrated, fully programmable, sigma-delta fractional-n synthesizer suitable for gprs multi-slot operation. except for the loop filter, the frequency synthesizer function, including a wideband vco, is completely on-chip. the reference frequency for the synthesizer is supplied by the integrated crystal oscillator circuitry. the 56-pin 8x8 rf land grid array (rflga?) device package and pin configuration are shown in figure 1. a functional block diagram is shown in figure 2. signal pin assignments, functional pin descriptions, and equivalent circuitry are provided in table 1.
data sheet i cx74063-34/-35/-36 2 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c nc nc lna1900in pdet lna1800in gndlna900 lna900in txinp txcpo vcc1 pdetvcc vcxo_en pco txena rxena 11 13 14 12 15 7 9 10 8 3 5 6 4 1 2 uhfbyp uhftune vccuhf vcc3 rxqn rxqp rxin rxip vcc4 vcctxvco tx900 tx1800/tx1900 txvco tune 56 54 53 55 52 50 49 51 48 46 45 47 44 lpfadj xtalbuf gndd vccd vccf xtal gndfn uhfcpo vccfn_cp sxena xtaltune data clk le vddbb 33 31 30 32 29 37 35 34 36 41 39 38 40 43 42 16 18 19 17 20 22 23 21 24 26 27 25 28 pavapc capqn capqp capin capip vcc2 txifn txifp txqn txqp txin txip bbvapc c1328 figure 1. cx74063-3x pinout C 56-pin rflga (8 x 8 mm) (top view) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 3 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 pa gain controller offset gen det vcc bbvapc pdet pdetvcc pavap c txin txip txqn txqp tx path sx txinp tx900 tx1800/tx1900 xtaltune xtal frac-n lo uhftune uhfcpo c900 indicates off-chip gsm lna dcs lna pcs lna rx path vga1 vga2 vga2 lna900 in lna1800in lna1900in capip capin capqp capqn rxip rxin rxqp rxqn dcoc vga1 dcoc dcoc dcoc dcoc dcoc + d1 pfd txvcotune txcpo filtn filtp txifp txifn gsm850/egsm9 00 dcs1800/pcs1900 d2 cp + ? xtalbuf pco vcxo_en le data clk figure 2. cx74063-3x transceiver block diagram data sheet i cx74063-34/-35/-36 4 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 1. cx74063-3x signal de scriptions (1 of 5) pin # name descriptio n equivalent circuit 1 rxena receiver enable input 2 txena transmitter enable input 3 pco bi-directional band select 4 vcxo_en vcxo enable pin 5 pdetvcc bias for the rf detector vref vout 6 vcc1 lna and tx charge pump supply vcc1 7 txcpo translational loop charge pump output 8 txinp translational loop feedback input 9 lna900in low band lna i nput for gsm850, egsm900 data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 5 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 1. cx74063-3x signal de scriptions (2 of 5) pin # name descriptio n equivalent circuit 10 gndlna900 low band lna emitter ground 11 lna1800in dcs lna input 12 pdet feedback input to power control loop 13 lna1900in pcs lna input 14 nc no connect no connect 15 nc no connect no connect 16 pavapc pa control output vout 17 bbvapc pa control baseband input data sheet i cx74063-34/-35/-36 6 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 1. cx74063-3x signal de scriptions (3 of 5) pin # name descriptio n equivalent circuit 18 txip tx i baseband input positive 19 txin tx i baseband input negative 20 txqp tx q baseband input positive 21 txqn tx q baseband input negative 22 txfp tx if filter output positive 23 txfn tx if filter output negative 24 vcc2 rx mixer and tx loop supply vcc2 25 capip capacitor filter i positive 26 capin capacitor filter i negative 27 capqp capacitor f ilter q positive 28 capqn capacitor f ilter q negative 29 lpfadj lpf frequency setting resistor 30 xtalbuf crystal oscillator buffer output 31 gndd synthesizer digital ground 32 vccd synthesizer digital supply vccd 33 vccf synthesizer analog supply and crystal oscillator supply vccf 34 xtal crystal input data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 7 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 1. cx74063-3x signal de scriptions (4 of 5) pin # name descriptio n equivalent circuit 35 gndfn synthesi zer analog ground 36 uhfcpo synthesizer charge pump output 37 vccfn_cp synthesizer charge pump supply vccfn_cp 38 sxena synthesizer enable input 39 xtaltune crystal oscillator varactor control 40 data serial bus data input 41 clk serial bus clock input 42 le serial bus latch enable input 43 vddbb digital cmos supply vddbb 44 uhfbyp bypass capa citor for uhf vco 45 uhftune uhf vco control input 46 vccuhf uhf vco supply vccuhf 47 vcc3 lo chain supply vcc3 data sheet i cx74063-34/-35/-36 8 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 1. cx74063-3x signal de scriptions (5 of 5) pin # name descriptio n equivalent circuit 48 rxqn receiver output q negative 49 rxqp receiver output q positive 50 rxin receiver output i negative 51 rxip receiver output i positive 52 vcc4 baseband supply vcc4 53 vcctxvco transmit vco supply vcctxvco 54 tx900 low band transmit vco 55 tx1800/tx1900 dcs and pcs transmit vco output 56 txvcotune transmit vco control input technical description the cx74063-3x transceiver contains the following sections, as shown in figure 2. ? receive section. includes three integrated lnas, a quadrature demodulator section that performs direct down conversion, baseband amplifier circuitry with i/q outputs, and three stages of dc offset correction. the receiver can be calibrated to optimize ip2 performance. ? synthesizer section. includes an integrated on-chip vco locked by a fractional-n synthesizer loop, and a crystal oscillator to supply the reference frequency. ? transmit section. the tx path is a translational loop architecture consisting of an i/q modulator, integrated high power vcos, offset mixer, programmable divider, pfd, and charge pump. the device also provides integrated gain controller for the pac loop, plus the bias generator for an external diode detector. a 3-wire serial interface controls the transceiver and synthesizer. the receiver gain control, as well as the division ratios and charge pump currents in the synthesizer and transmitter, can be programmed using 24-bit words. these 24-bit words are programmed using the 3-wire input signals clk, data, and le. to ensure that the data stays latched in power down mode, pin 43 (vddbb) must be continuously supplied with voltage. this pin is provided for the digital sections to allow power supply operation compatible with modern digital baseband devices. the txena, rxena, and sxena signals separately enable the cx74063-3x transmitter, receiver, and synthesizer sections. txena and rxena should be held low during programming. sxena should be held high during the programming of the r3 ip2 calibration register. (these timing signals are detailed in figures 9, 10, and 11.) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 9 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 receive section lna and quadrature demodulator three separate lnas are integrated to address different bands of operation. these lnas have separate single-ended inputs, which are externally matched to 50 ? . the gain is switchable between high (i.e., 15 db typical) and low (i.e., C5 db gsm, C7 db dcs, and C5 db pcs typical) settings. the lna outputs feed into a quadrature demodulator that downconverts the rf signals directly to baseband. two external 470 pf capacitors are required at the demodulator output to suppress the out-of- band blockers. baseband section an off-chip capacitor and three fixed poles of on-chip, low pass filtering provide rejection of strong in- and out-of-band interferers. in addition, a tunable, four-pole gmc filter provides rejection of the adjacent channel blockers. incorporated within the fixed-pole filters are two switchable gain stages of 18 db and 12 db gain steps, respectively. there is an additional programmable gain amplifier with a gain range from 0 to + 34 db, selectable in 2 db steps in the four-pole tunable filter. the final filter output feeds an amplifier with a gain range from 0 to 30 db, selectable in 6 db steps. there is an additional gain stage on the four-pole tunable filter output, the auxiliary gain stage, selectable at 0 db or + 6 db. the gain control ranges are shown in figure 3. recommended combinations of individual block gain settings are shown in table 22 for gsm900, table 23 for dcs1800, and table 24 for pcs1900. for added baseband interface flexibility, the four-pole filter, its associated variable gain amplifier (vga), and dc offset correction loop can be bypassed and turned off for current savings. in table 2 the typical locations of all eight receiver baseband poles are given. the final four poles are produced by the tunable gmc filter, as set by the external resistor (recommended value is 39.2 k ? , 1%) placed from pin 29 to ground. for these tunable poles, table 2 gives the pole location as a function of this resistor. dc offset correction three dc offset correction (dcoc) loops ensure that dc offsets, generated in the cx74063-3x, do not overload the baseband chain at any point. after compensation, the correction voltages are held on capacitors for the duration of the receive slot(s). internally, on-chip timing is provided to generate the track and hold (t_h) signals for the three correction loops. the timing diagram for the dc offset correction sequence with reference to the receive slot is shown in figure 4. a rising edge on either the rxena signal, selected via the serial interface, places the dc compensation circuitry in the track mode. the timing parameters for each of the three compensation loops, t t_h1 , t t_h2 , and t t_h3 , and the time between compensation start and the lna being turned on, t feena , are defined via an internal state machine. the state machine is preprogrammed with fixed default values, but may be readjusted via the serial interface. the timing parameters for the three compensation loops and the lna power-up are each independently defined, relative to the compensation start. therefore, they may be programmed to occur in any order, but the sequences shown in figure 4 and figure 5 are recommended. the device default timing is shown in figure 5, with a total time of 60 s. individual default timings are given in table 17. for user-programmed timing, the total time may be set as short as approximately 10 s when fref has a 13 mhz clock applied. however, the shortest recommended total time is approximately 30 s, since at the highest gain settings, the resulting dc may degrade as correction time is reduced. am suppression and ip2 calibration for direct conversion gsm applications, it is imperative to have extremely low second-order distortion. mathematically, second-order distortion of a constant tone generates a dc- term proportional to the square of the amplitude. a strong interfering amplitude-modulated (am) signal is therefore demodulated by second-order distortion in the receiver front end, and generates an interfering baseband signal. table 2. receive pole locations stage typical pole location (rad/sec) pole type C1.0 x 10 6 real (capacitors at pins 25-26 and 27-28 fixed at 470 pf) mixer + rc filter C1.65 x 10 6 real lpf1 (C0.91 x 10 6 ) j(1.35 x 10 6 ) conjugate (C0.91 x 10 6 ) x (39.2 k ? /r) real (adjust with resistor at pin 29) (C0.91 x 10 6 ) x (39.2 k ? /r) real (adjust with resistor at pin 29) vga1 + gmc filter [(C0.46 x 10 6 ) j(1.0 x 10 6 )] x (39.2 k ? /r) conjugate (adjust with resistor at pin 29) data sheet i cx74063-34/-35/-36 10 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c s092 40 db 22 db mixer + rc filter high low 10 db ?2 db lpf1 high low 6 db 0 db aux high low vga2 max (in 6 db steps) 30 db min 0 db ... ... vga1 +gmc max (in 6 db steps) 30 db min 0 db ... ... rxip rxin rxqp rxqn lna mixer + rc filter lpf1 vga2 vga1 + gmc filter + aux 15 db ?5 db gsm lna high low 4 db 2 db vga1 fine max mid min 0 db dcs lna high 15 db low ?7 db 5.0 db dcs1800 additional interstage losses gsm900 4.2 db pcs1900 6.2 db pcs lna high 15 db low ?5 db figure 3. gain control settings rxena 101953a 3_012902 t t_h1 t t_h2 t t_h3 front end enable t feena dc offset correction loop 1 (lna off) track mode hold mode (loop 1) dc offset correction loop 2 track mode dc offset correction loop 3 hold mode (loop 2) track mode hold mode (loop 3) start of rx slot note 1. t t_h1 , t t_h2 , t t_h3 , and t feena are programmed in register 2. (note 1) (note 1) (note 1) (lna on) (note 1) figure 4. dc offset correction timing (lna off dur ing all of the dc offset correction sequence) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 11 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 rxena 101953a 4_012902 t t_h1 t t_h2 t t_h3 front end enable t feena dc offset correction loop 1 (lna off) track mode hold mode (loop 1) dc offset correction loop 2 track mode dc offset correction loop 3 hold mode (loop 2) track mode hold mode (loop 3) note 1. t t_h1 , t t_h2 , t t_h3 , and t feena are programmed in register 2. (note 1) (note 1) (note 1) (lna on) start of rx slot (note 1) figure 5. dc offset correction timing (lna on dur ing part of the dc offset correction sequence) a commonly used measure for receiver second-order distortion is the second-order intercept point, ip2. for example, to ensure that the unwanted baseband signals are 9 db below the wanted signal required under the am suppression test for type approval (see 3gpp ts 51.010-1), an input ip2 of 43 dbm is required: the cx74063-3x receiver includes a circuit that minimizes second-order distortion. this ip2 calibration circuit effectively compensates any second-order distortion in the receive chain that would otherwise generate unwanted baseband signals in the presence of strong interfering signals. when calibrated correctly, the cx74063-3x ip2 meets the gsm am suppression test requirements in all bands with good margin. to calibrate ip2, apply a strong rf signal at the receiver input and observe the resulting dc voltage level change at the receiver i/q outputs. the exact frequency and level of the signal applied for the purpose of the calibration are not critical. the signal should, however, be within the receive band, but at least 6 mhz offset from the frequency to which the receiver is tuned. the level should be high enough to cause a notable dc shift at the i/q outputs. a recommended value is C30 dbm at the lna input, which applies to all three lnas. a set of i/q compensation coefficients can then be programmed to the device to minimize the dc voltage shift resulting from the second-order distortion. when the dc due to the interfering signal is minimized, the ip2 performance is optimized. note: sxena, pin 38, must be held high, and a clock signal must be present on xtal, pin 34, during the programming of the ip2 calibration coefficients in register 3, see table 18. the ip2 calibration is a one-time factory calibration that should be done for each band and each individual device for optimum performance. the determined coefficients must be stored in nonvolatile memory and programmed to the cx74063-3x upon each power-up as part of device initialization. there are on- chip registers that must be programmed through register 3 with the appropriate ip2 coefficients for the band in use. as long as a supply voltage is maintained on pin 43, vddbb, the ip2 coefficients for i lowband , i highband , q lowband , q highband , programmed to the device remain in the registers. after the supply voltage has been removed from vddbb, the coefficients must be re-programmed to the device again. receive/transmit i/q baseband signals . separate pins are provided for receive i/q outputs and transmit i/q inputs. however, for basebands that multiplex these signals, the receive i/q outputs and transmit i/q inputs can be tied together. synthesizer section the cx74063-3x includes a fully integrated uhf vco with an on-chip lc tank. a single sigma-delta fractional-n synthesizer can phase-lock the local oscillator used in both transmit and receive paths to a precision frequency reference input. fractional-n operation offers low phase noise and fast settling times, allowing for multiple slot applications such as gprs. the cx74063-3x frequency stepping function with a 3 hz resolution allows triple band operation in both transmit and receive bands using a fully integrated single integrated on-chip uhf vco. the fine synthesizer resolution allows direct compensation or adjustment for reference frequency errors. data sheet i cx74063-34/-35/-36 12 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c the fractional-n synthesizer consists of the following: ? vco ? high frequency prescaler ? n-divider with a sigma-delta modulator ? reference buffer and divider ? fast phase frequency detector and charge pump the user must provide the following three parameters: ? the reference divider value, from 1 to 15 ? the n-divider value, in a manner similar to an integer-n synthesizer ? a fractional ratio the generated frequency is given by the following equation: r f fn n f ref vco ? ? ? ? ? ? + + = 22 2 5 . 3 where: f vco = generated vco frequency n = n-divider ratio integer part fn = fractional setting r = r-divider ratio f ref = reference frequency uhf vco frequency setting for the receiver, to tune the receive frequency, f rx , set the vco frequency, f vco , as follows: ? rx vco f 2 3 f = for gsm850/900 ? rx vco f 4 3 f = for dcs1800 and pcs1900 for the transmitter vco frequency, refer to the equations shown in figure 6. digital frequency centering the cx74063-3x uses a novel technique whereby the uhf vco frequency range is re-centered each time the synthesizer is programmed. this technique is called digital frequency centering (dfc). the dfc technique: ? extends the vco frequency coverage ? speeds up settling time ? ensures robust performance since the vco is always operated at the center of its tuning range. each time the synthesizer is programmed, the dfc circuit is activated, and the vco is centered to the programmed frequency in less than 20 s. after this, normal phase locked loop (pll) operation is resumed and the fine settling of the frequency is finalized. the dfc typically adjusts the vco center frequency to within a few mhz and no more than 5 mhz offset, and presets the tuning voltage to the center of the range before the pll takes over. this speeds up frequency settling and ensures that the pll control voltage never operates close to the rails. + d2 d1 90 o x2 tx q where: f tx = f lo (2 d1 -- d2)/d1 gsm: f lo = (f vco )/3 dcs/pcs: f lo = (2f vco )/3 tx i phase detect tx vco external loop filter f tx x2 3 fractional-n pll uhf vco f vco l/c filter ext c1308 figure 6. transmitter frequency generation data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 13 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 the dfc is an adaptive circuit that corrects for any vco center frequency errors caused by variations of the integrated vco circuit, temperature, supply voltage, aging etc. the vco can be centered at any frequency in the range from 1.2 ghz to 1.55 ghz. once centered, the vco has a minimum analog tuning range of 30 mhz. no calibration or data storage is needed for dfc operation. it is activated by one of two events: ? when the synthesizer is programmed, the rising edge of the le signal starts the dfc cycle and, ? when changing the level of the sxena signal from low to high, thereby turning on the synthesizer, the rising edge of the sxena signal starts the dfc cycle. crystal oscillator a crystal oscillator is designed to provide the reference frequency for the synthesizer. as shown in figure 7, the oscillator uses an external crystal to generate an accurate oscillation frequency. the reference frequency can be changed through coarse tuning with an integrated capacitor array or fine tuning with the integrated varactor diode. the coarse tuning is done by switching in and out (using a digital word programmed via the serial interface) the capacitor network (cap_a and cap_b) located at the input of the integrated buffer. the fine tuning is done by providing a tuning voltage to the integrated varactor diode. table 20 describes the control bits. an output buffer is provided to drive the baseband circuitry (xtalbuf, pin 30). the vcxo and buffer circuitry are powered from pin 33 (vccf). when vccf is ramped to a voltage greater than 2.6 v, the output buffer powers on. the oscillator core powers up when pin 4 (vcxo_en) is set to logic 1. if pin 4 is tied permanently to logic 1, the r6 vcxo control register is set to a defined state by a power-on reset. pin 4 should be held low if an external reference oscillator is used. the buffer may be disabled by programming bit 3 in the sx1 control register (see table 13) to logic 0. transmit section to minimize the post-pa filtering requirements and any additional post-pa losses, the transmit path consists of a vector modulator within a frequency translation loop. the translation loop consists of the following: ? phase frequency detector (pfd) and charge pump ? mixer with an operating range of 800 mhz to 2 ghz ? an in-loop modulator ? two programmable dividers ? two transmit vcos translational loop the translational loop takes baseband analog i/q signals and modulates them with the mixed product of transmitter output and lo signal, as shown in figure 6. the unmodulated result is compared with a divided down lo at the pfd and the difference is used to control the transmit vco. the on-chip low pass filter (lpf) following the mixer attenuates the unwanted sidebands as well as harmonics. transmit vcos two on-chip transmit vcos are designed to meet gsm850, egsm900, dcs1800, and pcs1900 requirements. the transmit vcos use the same dfc technique as described in the synthesizer section to lock the translational loop. the rising edge on txena initializes the transmit dfc. vcxo_en (pin 4) xtal_buf (pin 30) to baseband [sx register 1 (bit 3)] buf_en baseband buffer vccf (pin 33) vccf (pin 33) xtal (pin 34) xtaltune (pin 39) pll c1337 cap_a 100 k ? cap_b 2 figure 7. vcxo block diagram data sheet i cx74063-34/-35/-36 14 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c from baseband coupler vcc2 power detector pavapc (pin 16) pdetvcc (pin 5) bbvapc (pin 17) pdet (pin 12) register 4 rx/tx control register (bit 21), pdetvcc txena (pin 2) pac delay timer 5 pf 0 = 0.5 v 1 = 1.0 v pa 8 c1338a bias generator 10 k ? + ? 1 figure 8. pa controller block diagram power amplifier gain controller the device contains an error amplifier/integrator to provide transmit burst control for an external power amplifier (pa). as shown in figure 8, when the device is connected to a pa, an rf detector, and a coupler, a loop is formed that controls the transmit power in a multi-band wireless application. the error amplifier amplifies and integrates the voltage difference between the rf detector output (pdet) and the power control input (bbvapc). the output of the integrator is fed to an internal gain shaper that drives the gain control input (pavapc) of the external rf pa. the device. provides a bandgap voltage (pdetvcc) which can be used as the supply voltage for the external peak detector and can source up to 200 a. the pa pre-bias is activated after a programmable delay and time-referenced from the rising edge of txena. the time delay is set using the serial interface. see table 19 for details. digital interface the transceiver and synthesizer are controlled by a single three-wire serial interface. the transmitter, receiver, and synthesizer are each enabled through external inputs according to typical timing requirements as shown in figures 10 and 11. band selection for the cx74063-3x is through the three-wire serial interface. the pco signal (pin 3) provides a band selection control output. dc offset calibration and front-end activation timing can also be controlled by an on-chip signal sequencer, precluding the need for separate control signals. all the logic and the three-wire interface inputs are referenced to the pco signal (pin 3). the rx/tx control register is used to program the transceiver and to preset other test word states by setting bit 22 as a logic 1. if any test words are to be altered from their preset states, bit 22 must be sent to the rx/tx control register again as a logic 0. typically, this is done only on power-up since the device has a zero-power standby mode that retains programmed test memory. there are eight additional registers used to program various functions of the cx74063-3x. the sx1 control register is used to program the fractional-n synthesizer and the sx2 fractional-n modulo register is used to program the modulus. four auxiliary registers are used to program the transceiver besides the rx/tx control register, and two 24-bit registers are used to program the synthesizer: ? sx1 synthesizer control ? sx2 fractional-n modulo ? rx/tx control ? r0 auxiliary control ? r2 dc offset timing ? r3 ip2 calibration ? r4 pac timing control ? r6 vcxo control ? r7 vcxo control sx1 control register . this register is used to program the fractional-n synthesizer, and set the values of the integral-n divider and the input-r divider. the polarity of the phase/frequency detector (pfd) may also be defined by this register. refer to table 13. data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 15 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 sx2 fractional-n modulo register . this register is used to program the 24-bit modulo of the fractional-n synthesizer. the data is a 22-bit binary coded decimal word that allows the pll to lock to precise frequencies. refer to table 14. rx/tx control register . this register is used to control divide ratios and charge pump currents in the transmitter, and to control gain in the receiver along with the band select function. refer to table 15. r0 auxiliary control register . this register is used to bypass the dc offset correction loops and the baseband filters. it also enables and disables the two on-chip transmit vcos and defines the directionality of the lo port, which allows an external vco or lo reference to be used or enables the internal vco to be monitored. refer to table 16. r2 dc offset timing register . this register sets the timing of the tracking of the three dc offset cancellation loops and the time at which the front end turns on relative to the rxena signal (pin 1). it allows the front-end to be enabled using the internal timer. refer to table 17. r3 ip2 calibration register . this register is used to perform 2 nd order intercept point (ip2) calibration by manually adjusting calibration coefficients. a total of four words need to be set: ip2 coefficients for i-high band, i-low band, q-high band, and q-low band. refer to table 18. the ip2 coefficient is eight bits long (including polarity) and is intended to be a factory calibration. an algorithm using a test tone needs to be used to determine the coefficient for each individual part. r4 pac timing control register . this register is used to set timing for the pac pedestal. refer to table 19. r6 and r7 vcxo control registers . these registers are used to control the tuning range and oscillation frequency of the vcxo. see tables 20 and 21, respectively. electrical and mechanical specifications the absolute maximum ratings of the cx74063-3x are provided in table 3. the recommended operating conditions are specified in table 4. electrical specifications are provided in tables 5 through 11. tables 12 through 21, and figures 9 through 11 provide the serial interface programming states, functions, and timing curves. receiver data is shown in tables 22 through 33 and illustrated in figures 12 through 20. transmit data is illustrated in figures 21 through 26. a typical application circuit using the cx74063-3x is shown in figure 27. the 56-pin rflga package dimensions are provided in figure 28 (-34 and -35 package options) and figure 29 (-36 package option). tape and reel dimensions are shown in figure 30 (-34 and -36 package options) and figure 31 (-35 package option). typical package case markings are explained in figure 32. package and handling information because this device package is sensitive to moisture absorption, it is baked and vacuum packed before shipment according to ipc j-std 033 guidelines. instructions on the shipping container label regarding exposure to moisture after the container seal is broken must be followed. these instructions adhere to ipc j-std 020a guidelines for handling moisture sensitive devices. if these instructions are not followed, problems related to moisture absorption may occur when the part is subjected to high temperature during solder assembly. the cx74063-3x transceiver is available in both low temperature and high temperature attachment packages. the rflga package for the low temperature attachment option provides a circular-shaped ground pad (cx74063-34). the rflga package for the high temperature options is available with both a circular-shaped ground pad and a four-quadrant, split center ground pad (CX74063-35 and cx74063-36, respectively). refer to figures 28 and 29 for package dimensions. guidelines for cx74063-3x low and high temperature attachment techniques are provided below. for additional details on attachment techniques, precautions, and recommended handling procedures, refer to the skyworks application note, pcb design & smt assembly guidelines for rflga packages , document number 103147. for the C34 low temper ature package option : if the cx74063-34 is attached in a reflow oven, the temperature ramp rate should not exceed 3 c per second. maximum temperature should not exceed 240 c and the time spent at a temperature that exceeds 235 c should be limited to less than 10 seconds. if the part is manually attached, precaution should be taken to ensure that the part is not subjected beyond a maximum temperature of 240 c or exceeds 235 c for more than 10 seconds. care must be taken when this product is attached, whether it is done manually or in a production solder reflow environment, to not heat the part beyond the recommended temperature. measure the temperature on the package itself by attaching thermocouples to the package body. for the C35 and C36 high te mperature package options : if the CX74063-35 or the cx74063-36 are attached in a reflow oven, the temperature ramp rate should not exceed 3 c per second. maximum temperature should not exceed 260 c and the time spent at a temperature that exceeds 255 c should be limited to less than 15 seconds. data sheet i cx74063-34/-35/-36 16 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c if the part is manually attached, precaution should be taken to ensure that the part is not subjected beyond a maximum temperature of 260 c or exceeds 255 c for more than 15 seconds. care must be taken when this product is attached, whether it is done manually or in a production solder reflow environment, to not heat the part beyond the recommended temperature. measure the temperature on the package itself by attaching thermocouples to the package body. production quantities of this product are shipped in a standard tape and reel format. for packaging details, refer to the skyworks application note, tape and reel , document number 101568. typical case markings for the cx74063-3x are shown in figure 31. electrostatic discharge the cx74063-3x contains class 1 devices. the following electrostatic discharge (esd) precautions are recommended: ? protective outer garments ? handle device in esd safeguarded work area ? transport device in esd shielded containers ? monitor and test all esd protection equipment ? treat the cx74063-3x as extremely sensitive to esd table 3. cx74063-3x absolute maximum ratings parameter minimum maximum units supply voltage (vcc) C0.3 +3.6 v ambient operating te mperature range C40 +95 c storage temperature range C50 +125 c input voltage range gnd vcc v maximum power dissipation 600 mw note : stresses above these absolute maximum ratings may cause permanent damage. these are stress ratings only and functional operation at these conditions is not implied. exposure to maximum rating conditions for extended periods may reduce device reliability. table 4. cx74063-3x recommended operating conditions parameter minimum typical maximum units lna input level (pins 9, 11, 13) rxen = off 10 dbm power supply 2.6 2.8 3.3 v digital power supply, vddbb 1.8 3.3 v operating junction temperature C40 +110 c operating ambient temperature C30 +85 c data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 17 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 5. power consumption specifications (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units total supply current: rx section, egsm/gsm850 tx section, egsm/gsm 850 (includes tx vco) synthesizer sect ion, egsm/gsm850 (includes uhf vco) rx section, dcs/pcs tx section, dcs/pcs (includes tx vco) synthesizer section, dcs/pcs (includes uhf vco) sleep mode i cc rxena=h; sxena=l txena=h; sxena=l sxena=h rxena=h; sxena=l txena=h; sxena=l sxena=h @ vcc = 3.3 v rxena=l; txena=l; sxena=l 41 121 39 49 126 39 20 48 137 46 58 143 46 100 ma ma ma ma ma ma a table 6. cx74063-3x electrical specificat ions C egsm/gsm850 receiver (1 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units input impedance. see figure 12 for unmatched input impedance. z in with external match 50 ? input operating freque ncy band 1 869 960 mhz receiver maximum voltage gain g rxmax highest gain mode 120 126 db receiver minimum voltage gain g rxmin lowest gain mode 11 17 db receiver gain temperature variation g temvar t a = C30 c to +85 c 4.5 db gain step ? a v 2 db gain step accuracy g step over range recommended in table 25 C0.75 +0.75 db gain variation versus frequency g freq over 869-894 mhz over 925-960 mhz 2 2 db db noise figure nf gain 1 g = 15/40/10/12/0/18 3.2 3.9 db noise figure (temperature) nf temp t a = +75 c t a = +85 c g = 15/40/10/12/0/18 5.0 5.2 db db data sheet i cx74063-34/-35/-36 18 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 6. cx74063-3x electrical specificat ions C egsm/gsm850 receiver (2 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units noise figure degradation in presence of blocker nf bloc with C26 dbm input blocker @ 3 mhz offset (ideal lo) internal lo g = 15/40/10/12/0/18 2 4 db db input 2nd order intercept point iip2 referred to lna input calibrated and measured at middle of egsm or gsm850 band. 50 65 dbm dc shift in presence of blocker am supp with C34 dbm @ 6 mhz offset g = 15/40/10/12/0/18 17 mv lo re-radiation @ lna input lore v @ wanted frequency C110 C100 dbm selectivity @ 3 mhz offset @ 1.6 mhz offset @ 600 khz offset @ 400 khz offset @ 200 khz offset t a = C30 c to +85 c 143 128 61 37 9 137 68 44 13 db db db db db i/q amplitude imbalance t a = C30 c to +85 c 1 db i/q phase imbalance t a = C30 c to +85 c C3 +3 degrees input 1 db compression point ip1db f = 200 khz, g = 15/40/-2/8/0/18 f = 400 khz, g = 15/40/-2/8/0/18 f = 600 khz, g = 15/40/10/12/0/18 f = 1.6 mhz, g = 15/40/10/12/0/18 f = 3.0 mhz, g = 15/40/10/12/0/18 C65 C45 C35 C32 C25 C60 C40 C30 C28 C22 dbm dbm dbm dbm dbm 3rd order intercept point @ +25 c iip3 f = 3.0 mhz g = 15/40/10/12/0/18 C15 C12 dbm 3rd order intercept point @ C20 c iip3 f = 3.0 mhz g = 15/40/10/12/0/18 C15 C12 dbm data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 19 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 6. cx74063-3x electrical specificat ions C egsm/gsm850 receiver (3 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units output offset voltage with dc offset corrected while lna is off t a = +85 c with dc offset corrected while lna is on g=15/40/10/12/0/18 t a = +85 c (60 s total dc correction time) 200 220 20 25 mv mv mv mv offset drift (long term) dcdrft1 50 ms after correction g = 15/40/10/12/0/18 100 mv offset drift (short term) dcdrft2 577 s after correction g = 15/40/10/12/0/18 10 mv baseband tunable active filter 3 db corner frequency (tunable) f c 80 100 khz corner frequency variation df c 39.2 k ? at pin 29 470 pf at pins 25-26 and 27-28 C11 +11 % receiver output stage differential output amplitude (pk/pk differential) vga2 = 30 db vga2 = 0 db 3.7 0.3 v v output common mode voltage t a = C30 c to +85 c vcc/2 C 0.1 vcc/2 vcc/2 + 0.1 v maximum current drive i out 0.5 ma output resistance r out rxena = h, rxena = l, differential rxena = l, single- ended 160 >1m 200 40k 240 ? ? ? output capacitance c out 1 pf note 1 : gain codes refer to lna/mixer /lpf1/vga1/aux/vga2 gains in db. data sheet i cx74063-34/-35/-36 20 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 7. cx74063-3x electrical specifica tions C dcs1800 receiver (1 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units input impedance see figure 13 for unmatched input impedance. z in with external match 50 ? input operating frequency ba nd 2 dcs rx band 1805 1880 mhz receiver maximum voltage gain g rxmax highest gain mode 117 123 db receiver minimum voltage gain g rxmin lowest gain mode 9 15 db gain step ? a v 2 db receiver gain temperature variation g tempvar t a = C30 c to +85 c 4.5 db gain step accuracy g step over range recommended in table 26 C0.75 +0.75 db gain variation versus frequency g freq over band 2 2 db noise figure nf gain 1 g = 15/40/10/12/0/18 3.6 4.3 db noise figure (temperature) nf temp t a = +75 c t a = +85 c 5.4 5.6 db noise figure degradation in presence of blocker nf bloc with C30 dbm input blocker @ 3 mhz offset (ideal lo) internal lo g = 15/40/10/12/0/18 2 4 db db input 2nd order intercept point iip2 referred to lna input calibrated and measured at middle of dcs1800 band. 50 65 dbm dc shift in presence of blocker am supp with C33 dbm @ 6 mhz offset g = 15/40/10/12/0/18 17 mv lo re-radiation @ lna input lore v @ wanted frequency C110 C100 dbm selectivity @ 3 mhz offset @ 1.6 mhz offset @ 600 khz offset @ 400 khz offset @ 200 khz offset t a = C30 c to +85 c 143 128 61 37 9 137 68 41 13 db db db db db i/q amplitude imbalance t a = C30 c to +85 c 1 db i/q phase imbalance t a = C30 c to +85 c C3 +3 degrees data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 21 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 7. cx74063-3x electrical specifica tions C dcs1800 receiver (2 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units input 1 db compression point ip1db f = 200 khz, g = 15/40/-2/8/0/18 f = 400 khz, g = 15/40/-2/8/0/18 f = 600 khz, g = 15/40/10/12/0/18 f = 1.6 mhz, g = 15/40/10/12/0/18 f = 3.0 mhz, g = 15/40/10/12/0/18 C65 C45 C35 C32 C25 C60 C40 C30 C28 C22 dbm dbm dbm dbm dbm 3rd order intercept point @ +25 c iip3 f = 3.0 mhz g = 15/40/10/12/0/18 C15 C12 dbm 3rd order intercept point @ C20 c iip3 f = 3.0 mhz g = 15/40/10/12/0/18 C15 C12 dbm output offset voltage with dc offset corrected while lna is off t a = + 85 c with dc offset corrected while lna is on g = 15/40/10/12/0/18 t a = + 85 c (60 s total dc correction time) 200 220 20 25 mv mv mv mv offset drift (long term) dcdrft1 g = 15/40/10/12/0/18 50 ms after correction 100 mv offset drift (short term) dcdrft2 g = 15/40/10/12/0/18 577 s after correction 10 mv baseband tunable active filter 3 db corner frequency (tunable) f c 80 100 khz corner frequency variation df c 39.2 k ? at pin 29 470 pf at pins 25-26 and 27-28 C 11 + 11 % data sheet i cx74063-34/-35/-36 22 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 7. cx74063-3x electrical specifica tions C dcs1800 receiver (3 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units receiver output stage differential output amplitude (pk/pk differential) vga2 = 30 db vga2 = 0 db 3.7 0.3 v v output common mode voltage vcc/2 C 0.1 vcc/2 vcc/2 + 0.1 v maximum current drive i out 0.5 ma output resistance r out rxena = h, rxena = l, differential, rxena = l, single- ended 160 >1m 200 40k 240 ? ? ? output capacitance c out 1 pf note 1: gain codes refer to lna/mixer /lpf1/vga1/aux/vga2 gains in db. table 8. cx74063-3x electrical specifica tions C pcs1900 receiver (1 of 3) (t a =2 5 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units input impedance. see figure 14 for unmatched input impedance. z in with external match 50 ? input operating frequency ba nd 3 pcs rx band 1930 1990 mhz receiver maximum voltage gain g rxmax highest gain mode 117 123 db receiver minimum voltage gain g rxmin lowest gain mode 7 13 db receiver gain temperature variation g tempvar t a = C30 c to +85 c 4.5 db gain step ? a v 2 db gain step accuracy g step over range recommended in table 27 C0.75 +0.75 db gain variation versus frequency g freq over band 3 2 db noise figure nf gain 1 g = 15/40/10/14/0/18 4.2 4.9 db noise figure (temperature) nf temp t a = +75 c t a = +85 c 6.0 6.2 db noise figure degradation in presence of blocker nf bloc with C30 dbm input blocker @ 3mhz offset (ideal lo) internal lo g = 15/40/10/14/0/18 2 4 db db data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 23 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 8. cx74063-3x electrical specifica tions C pcs1900 receiver (2 of 3) (t a =2 5 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units input 2nd order intercept point iip2 referred to lna input calibrated and measured at middle of pcs1900 band 50 65 dbm dc shift in presence of blocker am supp with C33 dbm @ 6 mhz offset g = 15/40/10/14/0/18 17 mv lo re-radiation @ lna input lore v @ wanted frequency C110 C100 dbm selectivity @ 3 mhz offset @ 1.6 mhz offset @ 600 khz offset @ 400 khz offset @ 200 khz offset t a = C30 c to +85 c 143 128 61 37 9 137 68 41 13 db db db db db i/q amplitude imbalance t a = C30 c to +85 c 1 db i/q phase imbalance t a = C30 c to +85 c C3 +3 degrees input 1 db compression point ip1db f = 200 khz, g = 15/40/-2/8/0/18 f = 400 khz, g = 15/40/-2/8/0/18 f = 600 khz, g = 15/40/10/14/0/18 f = 1.6 mhz, g = 15/40/10/14/0/18 f = 3.0 mhz, g = 15/40/10/14/0/18 C65 C45 C35 C32 C25 C60 C40 C30 C28 C22 dbm dbm dbm dbm dbm 3rd order intercept point @ +25 c iip3 f = 3.0 mhz g = 15/40/10/14/0/18 C15 C12 dbm 3rd order intercept point @ C20 c iip3 f = 3.0 mhz g = 15/40/10/14/0/18 C15 C12 dbm output offset voltage with dc offset corrected while lna is off t a = +85 c with dc offset corrected while lna is on t a = +85 c g = 15/40/10/12/0/18 (60 s total dc correction time) 200 220 20 25 mv mv mv mv data sheet i cx74063-34/-35/-36 24 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 8. cx74063-3x electrical specifica tions C pcs1900 receiver (3 of 3) (t a =2 5 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condition (note 1) min typical max units offset drift (long term) dcdrft1 50 ms after correction g = 15/40/10/14/0/18 100 mv offset drift (short term) dcdrft2 577 s after correction g = 15/40/10/14/0/18 10 mv baseband tunable active filter 3 db corner frequency (tunable) f c 80 100 khz corner frequency variation df c 39.2 k ? at pin 29 470 pf at pins 25-26 and 27-28 C11 +11 % receiver output stage differential output amplitude (pk/pk differential) vga2 = 30 db vga2 = 0 db 3.7 0.3 v v output common mode voltage vcc/2 C 0.1 vcc/2 vcc/2 + 0.1 v maximum current drive i out 0.5 ma output resistance r out rxena = h, rxena = l, differential, rxena = l, single- ended 160 >1m 200 40k 240 ? ? ? output capacitance c out 1 pf note 1: gain codes refer to lna/mixer /lpf1/vga1/aux/vga2 gains in db. table 9. cx74063-3x electrical specifications C transmitter (1 of 4) (t a =2 5 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units i/q modulator input impedance z in txena = h, differential, txena = l, differential, txena = l, single- ended 400k >1m 60k ? ? ? input signal level differential 0.8 1 1.2 vp-p input common mode voltage range v cm 0.85 1.35 vcc C 1.3 v input frequency 3 db bandwidth 3 mhz input common mode rejection ratio f in = 100 khz f in = 1 mhz 65 45 75 55 db output operating frequency f out 70 130 mhz output impedance z out per side 170 200 230 ? output voltage v out C33 dbv data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 25 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 9. cx74063-3x electrical specifications C transmitter (2 of 4) (t a =2 5 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units i/q modulator (continued) output noise power n o @ 10 mhz offset @ 1.8 mhz offset C132 C130 C128 C126 dbc/hz dbc/hz lo suppression 30 35 dbc sideband suppression 30 35 dbc translational loop spurious modulation 2nd order modulation 3rd order C70 C60 C40 C55 dbc dbc transmit frequency (input from vco) f tx 800 2000 mhz if frequency f if 70 130 mhz transmit input power p in with external 50 ? termination C20 C15 C10 dbm transmit input impedance z in 300// 0.3 ? // pf transmitter output phase noise (includes tx vco and lo pll) n o @ 400 khz offset @ 1.8 mhz offset @ 10 mhz offset egsm/gsm850 @ 20 mhz offset egsm/gsm850 @ 20 mhz offset dcs/pcs C120 C130 C152 C164 C156 C118 C124 C150 C162 C154 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz tx phase error tx pherr rms (employs reference frequency source, and loop filters as shown in the reference design) 2.0 degrees charge pump output current: high impedance source/sink i out rx/tx control register bits s17 s16 cp = 0 0 cp = 0 1 cp = 1 0 cp = 1 1 0.5 0.75 1.0 1.25 ma ma ma ma charge pump current variation 0.3 v cpo vcc C 0.5 20 % charge pump current variation over temperature 0.3 v cpo vcc C 0.5 t a = C30 c to +85 c 10 % d1 divide ratio range 9 12 d2 divide ratio 1 2 tx mixer lo leakage txmix leakage tx mixer 50 ? terminated C60 dbm data sheet i cx74063-34/-35/-36 26 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 9. cx74063-3x electrical specifications C transmitter (3 of 4) (t a =2 5 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units low band translation loop vco center frequency f c t a = C30 c to +85 c 800 930 mhz digital frequency centering resolution e dfc 2.5 mhz digital frequency centering time t dfc from rising edge of txena (13 mhz clock frequency) 12 20 s digital frequency centering voltage v dfc control voltage at end of dfc/start of analog lock vcc/2 C 0.2 vcc/2 vcc/2 + 0.2 v analog frequency control range f max C f min 0.5 < v ctl < 2.2 20 mhz absolute control sensitivity k vco (0.9 v < v ctl and 1.9 v > v ctl ) 820 mhz < f c < 850 mhz 870 mhz < f c < 915 mhz 16 18 21 25 26 32 mhz/v mhz/v output harmonics 2nd harmonic 3rd harmonic C50 C 55 C30 C30 dbc dbc phase noise @ 400 khz offset @ 20 mhz offset C125 C164 C120 C162 dbc/hz dbc/hz output vswr with external 50 ? match 2:1 pushing 2 4 mhz/v pulling vswr 2:1 4 mhz output power p out f out = 897.5 mhz with external 50 ? match 10.5 11.5 12.5 dbm output power temperature variation t a = C30 c to +85 c 0.7 db high band translation loop vco center frequency f c t a = C30 c to +85 c 1700 1930 mhz digital frequency centering resolution e dfc 6 mhz digital frequency centering time t dfc from rising edge of txena (13 mhz clock frequency) 12 20 s digital frequency centering voltage v dfc control voltage at end of dfc/start of analog lock vcc/2 C 0.2 vcc/2 vcc/2 + 0.2 v data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 27 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 9. cx74063-3x electrical specifications C transmitter (4 of 4) (t a =2 5 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units high band translation loop vco (continued) analog frequency control range f max C f min 0.5 < v ctl < 2.2 20 mhz absolute control sensitivity k vco 1710 mhz < f c < 1785 mhz 1850 mhz < f c < 1910 mhz 0.9 v < v ctl and 1.9 v > v ctl 14 19 18 23 22 27 mhz/v mhz/v output harmonics 2nd harmonic 3rd harmonic C50 C55 C30 C30 dbc dbc phase noise @ 400 khz offset @ 20 mhz offset C125 C158 C120 C155 dbc/hz dbc/hz output vswr with external 50 ? match 2:1 pushing 2 4 mhz/v pulling vswr 2:1 4 mhz output power p out f out = 1747.5 mhz with external 50 ? match 5.5 7 8.5 dbm output power variation t a = C30 c to +85 c 1 db pa gain controller pavapc output swing 0.22 vcc C 0.3 v pavapc offset voltage txena = h 0.68 v pavapc sink current i sink 550 a pavapc source current i source 750 a open loop gain g 104 111 db input common mode range 0 2.7 v pdetvcc source current i pdetvcc 200 a pdetvcc output voltage pdetvcc = 0 (bit 21 of rx/tx control register) pdetvcc = 1 (bit 21 of rx/tx control register) 0.5 1.0 v v output load 10pf // 10k ? data sheet i cx74063-34/-35/-36 28 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 10. cx74063-3x electrical specifica tions C synthesizer (1 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units prescaler operating input frequency 1000 1700 mhz reference input frequency 10 13 26 mhz phase detector frequency 13 15 mhz external crystal oscillator input sensitivity C15 +3 dbm reference oscillator sensitivity 0.4 vcc v peak in-band phase noise measured within the loop bandwidth C85 dbc/hz charge pump output current (can be programmed in four steps) v cp = vccfn_cp/2 (sx1 control register, bit[6:5] = 00) v cp = vccfn_cp/2 (sx1 control register, bit[6:5] = 01) v cp = vccfn_cp/2 (sx1 control register, bit[6:5] = 10) v cp = vccfn_cp/2 (sx1 control register, bit[6:5] = 11) 100 200 300 400 a a a a charge pump leakage current 0.5 < v cp < vccfn_cp C 0.5 0.1 na charge pump sink versus source mismatch v cp = vccfn_cp/2 5 % charge pump current versus voltage 0.5 < v cp < vccfn_cp C 0.5 10 % charge pump current versus temperature v cp = vccfn_cp/2 t a = C30 c to +85 c 10 % uhf vco center frequency f c t a = C30 c to +85 c 1200 1550 mhz digital frequency centering resolution e dfc 2 mhz digital frequency centering time t dfc from rising edge of sxena or le when programming sx word (13 mhz clock frequency) 12 20 s digital frequency centering voltage v dfc control voltage at end of dfc/start of analog lock v ccuhf /2 C 0.2 v ccuhf /2 v ccuhf /2 + 0.2 v analog frequency control range f max C f min 0.5 < v ctl < 2.2 30 mhz data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 29 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 10. cx74063-3x electrical specifica tions C synthesizer (2 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units uhf vco (continued) relative control sensitivity k vco /f c after dfc, within the range of e vctl 1200 mhz < f c < 1300 mhz 1300 mhz < f c < 1400 mhz 1400 mhz < f c < 1475 mhz 1475 mhz < f c < 1550 mhz 1.3 1.5 1.7 1.9 1.7 2.0 2.2 2.4 2.1 2.4 2.6 2.8 %/v %/v %/v %/v absolute control sensitivity k vco v dcf + e vctl , min < v ctl and v dcf + e vctl , max > v ctl 1200 mhz < f c < 1300 mhz 1300 mhz < f c < 1400 mhz 1400 mhz < f c < 1475 mhz 1475 mhz < f c < 1550 mhz 15 19 24 28 21 27 32 36 28 34 39 44 mhz/v mhz/v mhz/v mhz/v phase noise @ 400 khz offset @ 3 mhz offset C123 C140 C121 C137 dbc/hz dbc/hz slow center frequency drift ? f c / ? t t a = C30 c to + 85 c C5 +5 mhz/sec 26 mhz crystal oscillator operating frequency 26 mhz buffer output frequency 13 mhz phase noise: @ 100 hz @ 1 khz @ 10 khz C98 C127 C145 dbc/hz dbc/hz dbc/hz clock jitter 16 ps spurious rejection C20 C15 dbc digital tuning (note 1) 45 70 ppm analog tuning (note 1) v tune = 0.05 to 2.5 v 23 ppm analog varactor voltage range 0 vcc v analog varactor dc impedance 1 m ? data sheet i cx74063-34/-35/-36 30 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 10. cx74063-3x electrical specifica tions C synthesizer (3 of 3) (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units 26 mhz crystal oscillator (continued) supply voltage dependence 2.8 0.1 v 1 2 ppm/v operating current (start) @ 26 mhz 2600 a operating current (equilibrium) @ 26 mhz 2600 a voltage swing @ crystal 1.1 vpp voltage swing @ buffer 1.1 vpp buffer output load 10pf || 10 k ? start-up time 4 ms note 1 : using a crystal with equi valent 6 mh inductor and esr 100 ? . data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 31 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 11. cx74063-3x electrical specifications C digital interface (t a = 25 c, vcc = 2.8 v unless otherwise noted) parameter symbol test condi tion min typical max units data to clock setup time (note 1) t cs 30 ns data to clock hold time (note 1) t ch 10 ns clock pulse width high (note 1) t cwh 30 ns clock pulse width low (note 1) t cwl 30 ns clock to load enable setup time (note 1) t es 30 ns load enable pulse width (note 1) t ew 50 ns le falling edge to clock rising edge (note 1) t efc 30 ns rxena setup time txena setup time sxena setup time 30 30 30 ns ns ns high level input voltage for rxena, txena, data, clk, le, pco, vcxo_en, and sxena v ih 0.8 vddbb v low level input voltage for rxena, txena, data, clk, le, pco, vcxo_en, and sxena v il 0.2 vddbb v high level input current for rxena, txena, data, clk, le, pco, vcxo_en, and sxena i ih C1 +1 a low level input current for rxena, txena, data, clk, le, pco, vcxo_en, and sxena i il C1 +1 a digital input pin capacitance for rxena, txena, data, clk, le, pco, vcxo_en, and sxena c id 10 pf high level output voltage for pco v oh i oh = C1.0 ma vddbb C 0.4 v low level output voltage for pco v ol i ol = 1.0 ma 0.4 v digital output pin load capacitance for pco c ld 15 pf note 1 : see figure 9. data sheet i cx74063-34/-35/-36 32 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c serial interface programming table 12. control and output states address bits register b6 b5 b4 b3 b2 b1 b0 sx register 1: synthesize r control x x x x x 0 0 sx register 2: fractional-n modulo x x x x x 1 0 rx/tx control register x x x x x 1 1 r0: auxiliary control x x x 0 0 0 1 r2: dc offset timing x x x 1 0 0 1 r3: ip2 calibration x 0 0 1 1 0 1 r4: pac timing control x 0 1 1 1 0 1 r6: vcxo control 0 1 0 1 1 0 1 r7: vcxo control 1 1 0 1 1 0 1 table 13. sx register 1: synt hesizer control functions symbol function state description addr address bits [1:0]. must be set to 00b (see table 12) en enable mode [2] 0 enables synthesizer 1 disables synthesizer buf_en buffer enable [3] 0 sets buffer to off state 1 sets buffer to on state sp phase detector output polarity [4] 0 sets phase detector output for negative vco gain 1 sets phase detector output for positive vco gain sc charge pump output current [6:5] bit [6:5] 0 0 sets charge pump current to 100 a 0 1 sets charge pump current to 200 a 1 0 sets charge pump current to 300 a 1 1 sets charge pump current to 400 a rsvd reserved bit [8:7]: set bit 8 = 1, bit 7 = 0 n main divider [19:9] sets 11-bit main divider ratio range (642047) r reference divider [23:20] sets 4-bit reference divider ratio range (115) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 33 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 14. sx register 2: fractional-n modulo symbol function state description addr address bits [1:0]. must be set to 10b (see table 12) fn fractional-n modulo [23:2] se ts fractional-n modulo up to 2 22 range (04,194,303) table 15. rx/tx control register (1 of 2) symbol function state description addr address bits [1:0]. must be set to 11b (see table 12) lna lna gain step control [2] 0 selects low gain mode of lna 1 selects high gain mode of lna mix mixer gain step [3] 0 selects low gain mode of rx mixer 1 selects high gain mode of rx mixer lpf1 1st lpf gain step [4] 0 selects low gain mode of the first active lpf 1 selects high gain mode of the first active lpf vga2 vga2 gain steps [7:5] bit 7 to bit 5 pr ogram the vga2 gain in 6 db increments bit 7, bit 6, bit 5 0 0 0 sets the gain to 30 db 0 0 1 sets the gain to 24 db 0 1 0 sets the gain to 18 db 0 1 1 sets the gain to 12 db 1 0 0 sets the gain to 6 db 1 0 1 sets the gain to 0 db 1 1 0 not used 1 1 1 not used aux auxiliary gain [8] 0 sets 0 db auxiliary gain post gmc filter 1 sets 6 db auxiliary gain post gmc filter vga1 vga1 gain steps [11:9] bit 11 to bit 9 program the vga1 g ain in the following increments: bit 11, bit 10, bit 9 0 0 0 sets the gain to 0 db 0 0 1 sets the gain to 24 db 0 1 0 sets the gain to 12 db 0 1 1 not used 1 0 0 sets the gain to 6 db 1 0 1 sets the gain to 30 db 1 1 0 sets the gain to 18 db 1 1 1 not used vga1fine vga1 fine gain step [13:12] bit 13 a nd bit 12 program vga1 in 2 db increments bit 13, bit 12 0 0 sets gain to 0 db 0 1 sets gain to 4 db 1 0 sets gain to 2 db 1 1 not used data sheet i cx74063-34/-35/-36 34 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 15. rx/tx control register (2 of 2) symbol function state description softsel software band select [15:14] bit 15, bit 14 0 0 not used 0 1 selects egsm/gsm850, pco = 0 1 0 selects dcs, pco = 1 1 1 selects pcs, pco = 1 txcp tx charge pump bits [17:16] tran slational loop charge pump current setting bit 17, bit 16 0 0 sets txcp to 0.5 ma 0 1 sets txcp to 0.75 ma 1 0 sets txcp to 1.0 ma 1 1 sets txcp to 1.25 ma txd1 tx divider d1 [19:18] tran slational loop d1 divider setting bit 19, bit 18 0 0 sets d1 to 9 0 1 sets d1 to 11 1 0 sets d1 to 10 1 1 sets d1 to 12 txd2 tx divider d2 [20] translational loop d2 divider setting: 0 sets d2 to 1 1 sets d2 to 2 pdetvcc power detector bias [21] bit [21] sets bias voltage for the schottky diode pair: 0 = 0.5 v 1 = 1.0 v preena load default words [22] 0 allows changing contents of r0 to r7 1 allows loading default words into r0 to r7 upon power up, program rx/tx control register with preena = 1 to load the default words into r0 to r5. if changing the default words is required, program rx/tx control register with preena = 0 and then program any or all of r0 to r5. preena should also be set to 0 when sending sx r1, sx r2, and rx/tx control register words before each time slot in normal operation. the data is stored in r0 to r5 as long as vddbb (pin 43) is supplied with power. nu not used [23] not used data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 35 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 16. register 0: auxiliary control symbol function state description default (binary) addr address bits [3:0]. must be set to 0001b (see table 12) gmc_byp bypass gmc stage [4] 0 enables gmc filter stage 1 disables and bypasses gmc filter stage 0 sk_byp bypass s-k stage [5] 0 en ables sallen-key filter stage 1 disables and bypasses sallen-key filter stage 0 dc_byp1 bypass first dc oc loop [6] 0 enables first dc offset correction loop 1 disables and bypasses first dc offset correction loop 0 dc_byp2 bypass second dc oc loop [7] 0 enables second dc offset correction loop 1 disables and bypasses second dc offset correction 0 dc_byp3 bypass second dc oc loop [8] 0 enables third dc offset correction loop 1 disables and bypasses third dc offset correction 0 nu not used [9] not used 0 tvcoen txvco select [10] 0 disables txvco 1 enables txvco via txena (pin4) 1 rsvd reserved [12:11] reserved, must be programmed to default value 10 nu not used [13] not used 0 rsvd reserved [14] reserved, must be programmed to default value 0 rsvd reserved [15] reserved, must be programmed to default value 0 dfcpllena dfc enable [16] 0 disables dfc 1 enables dfc 1 uhfvcoena uhfvco enable [17] 0 disables internal uhf vco 1 enables internal uhf vco 1 rsvd reserved[20:18] reserved, must be programmed to default value 011 calena enable ip2 cal [21] 0 disables ip2 calibration 1 enables ip2 calibration 1 nu not used[22] not used 0 nu not used[23] not used 0 data sheet i cx74063-34/-35/-36 36 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 17. register 2: dc offset timing symbol function state description default (binary) addr address bits [3:0]. must be set to 1001b (see table 12) dcocl1 dcoc control [7:4] tracking ti ming for dcoc1 (tt_h1 = (dcocl1 x 64 x r)/fref ) (note 1) 0100 (20 s with 13 mhz f ref ) dcocl2 dcoc control [12:8] tracking ti ming for dcoc2 (tt_h2 = (dcocl2 x 64 x r)/fref ) (note 1) 01100 (60 s with 13 mhz f ref ) dcocl3 dcoc control [16:13] tracking ti ming for dcoc3 (tt_h3 = (dcocl3 x 128 x r)/fref ) (note 1) 0110 (60 s with 13 mhz f ref ) feena_tim feena relative to initial track [20:17] front end enable timing (tfeena = (feena_tim x 128 x r)/fref ) (note 1) 0100 (40 s with 13 mhz f ref ) nu not used [21] not used 0 nu not used [22] not used 0 nu not used [23] not used 0 note 1 : see figure 4 and figure 5. table 18. register 3: ip2 calibration symbol function state description addr address bits [5:0]. must be set to 001101b (see table 12) addr_sel channel selection [6] 0 selects q channel 1 selects i channel rsvd reserved [7] must be se t to 1 for correct operation corr_data ip2 correction coefficient [15:8] c oefficient for adjustment of receiver ip2 bit [15] sets polarity: 0 = positive 1 = negative bit [14:8] 1111111 minimum correction ? ? ? 0000000 maximum correction bit [14] = msb bit [8] = lsb nu not used [23:16] not used data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 37 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 19. register 4: pac timing control symbol function state description default (binary) addr address bits [5:0]. must be set to 011101b (see table 12) rsvd reserved [11:6] reserved. mu st be set to default value. 000010 pac_time pac timing control [19:12] bit [19:12] sets timing for pac pedestal. when all bits = 0, no pedestal. bit [12] = msb = 1024/f pfd = 78.7 s for f pfd = 13 mhz bit [19] = lsb = 8/f pfd = 0.615 s for f pfd = 13 mhz 10011010 = 54.769 s rsvd reserved [23:20] reserved. mu st be set to default value. 0100 table 20. register 6: vcxo control symbol function description internal power-on value (binary) recommended operational value (binary) addr address bits [6:0]. must be set to 0101101b (see table 12) cap_a bit [11:7] capacitor a arra y control. binary weighted. bit [11] = lsb = 1/8 pf bit [7] = msb = 2 pf array composition = 2 pf, 1 pf, 0.5 pf, 0.25 pf, 0.125 pf 00001 cap_b bit [15:12] capacitor b arra y control. binary weighted. bit [15] = lsb = 1/32 pf bit [12] = msb = 1/4 pf array composition = 0.25 pf, 0.125 pf, 0.065 pf, 0.03125 pf 0000 determined during a one- time factory calibration rsvd bit [23:16] reserved 00000000 00000000 note : programmed values in this register are not maintained with vddbb (pin 43). data sheet i cx74063-34/-35/-36 38 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 21. register 7: vcxo control symbol function description internal power-on value (binary) recommended operational value (binary) addr address bits [6:0]. must be set to 1101101b (see table 12) i_vcxo bit [10:7] negative resist ance current control. binary weighted. negative logic (on = low, off = high) bit [10] = lsb = 8 a bit [7] = msb = 64 a stepped values = 64 a, 32 a, 16 a, 8 a 0101 1001 rsvd bit [23:11] reserved. must be set to default value. 0000000000000 0000000001110 (must use) note : programmed values in this register are not maintained with vddbb (pin 43). s0 s1 s22 s23 data clock le t cs t cwh t cwl t es t ch t ew c898 figure 9. serial data input timing diagram for transceiver data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 39 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 7 0 1 2 3 4 5 6 rxena sxena txena le 120 s 20 s 50 s 10 s mon internal dcoc 1 internal feena 240 s 240 s 10 s (note 1) internal dcoc 2 internal dcoc 3 40 s 60 s rx tx offset gen timing pavapc 0.7 v note 1: this timing depends on circuitry other than the cx74063. trsw enable 25 s (note 1) tx i/q fref (not to scale) c1330 pa ramp voltage pac_time figure 10. cx74063-3x signal timing example (normal operation) fref (not to scale) note 1. le should be low before the next clock goes high. note 2. vddbb, pin 43, is required to hold the register settings. if vddbb is not maintained high, the power-on programming sequence needs to be added in front of each normal slot programming sequence. c1329 sxena data preset=1 preset=0 band=gsm gsm ip2 i gsm ip2 q dcs/pcs ip2 i dcs/pcs ip2 q dcoc timing preset=0 band=dcs/pcs clk le vcxo control 2 vcxo control 1 note 1 note 1 vddbb (pin 43) note 2 figure 11. cx74063-3x register programming sequence and timing example (initialization after power up) data sheet i cx74063-34/-35/-36 40 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c receiver data table 22. recommended egsm900/gsm850 agc data (1 of 2) (agc setpoint = C25.2 dbv = 55.0 mvrms) antenna input (dbm) i/q output (dbv) from to external front end losses (db) lna (db) mixer (db) lpf (db) vga1 (db) vga1 fine (db) aux (db) vga2 (db) internal inter- stage losses (db) total voltage gain (db) from to C110 C108 C4.0 15 40 10 18 4 0 18 C4.2 96.8 C26.2 C24.2 C108 C106 C4.0 15 40 10 18 2 0 18 C4.2 94.8 C26.2 C24.2 C106 C104 C4.0 15 40 10 18 0 0 18 C4.2 92.8 C26.2 C24.2 C104 C102 C4.0 15 40 10 12 4 0 18 C4.2 90.8 C26.2 C24.2 C102 C100 C4.0 15 40 10 12 2 0 18 C4.2 88.8 C26.2 C24.2 C100 C98 C4.0 15 40 10 12 0 0 18 C4.2 86.8 C26.2 C24.2 C98 C96 C4.0 15 40 10 6 4 0 18 C4.2 84.8 C26.2 C24.2 C96 C94 C4.0 15 40 10 6 2 0 18 C4.2 82.8 C26.2 C24.2 C94 C92 C4.0 15 40 10 6 0 0 18 C4.2 80.8 C26.2 C24.2 C92 C90 C4.0 15 40 10 0 4 0 18 C4.2 78.8 C26.2 C24.2 C90 C88 C4.0 15 40 10 0 2 0 18 C4.2 76.8 C26.2 C24.2 C88 C86 C4.0 15 40 10 0 0 0 18 C4.2 74.8 C26.2 C24.2 C86 C84 C4.0 15 40 C2 6 4 0 18 C4.2 72.8 C26.2 C24.2 C84 C82 C4.0 15 40 C2 6 2 0 18 C4.2 70.8 C26.2 C24.2 C82 C80 C4.0 15 40 C2 6 0 0 18 C4.2 68.8 C26.2 C24.2 C80 C78 C4.0 15 40 C2 0 4 0 18 C4.2 66.8 C26.2 C24.2 C78 C76 C4.0 15 40 C2 0 2 0 18 C4.2 64.8 C26.2 C24.2 C76 C74 C4.0 15 40 C2 0 0 0 18 C4.2 62.8 C26.2 C24.2 C74 C72 C4.0 15 22 10 0 4 0 18 C4.2 60.8 C26.2 C24.2 C72 C70 C4.0 15 22 10 0 2 0 18 C4.2 58.8 C26.2 C24.2 C70 C68 C4.0 15 22 10 0 0 0 18 C4.2 56.8 C26.2 C24.2 C68 C66 C4.0 15 22 C2 6 4 0 18 C4.2 54.8 C26.2 C24.2 C66 C64 C4.0 15 22 C2 6 2 0 18 C4.2 52.8 C26.2 C24.2 C64 C62 C4.0 15 22 C2 6 0 0 18 C4.2 50.8 C26.2 C24.2 C62 C60 C4.0 15 22 C2 0 4 0 18 C4.2 48.8 C26.2 C24.2 C60 C58 C4.0 15 22 C2 0 2 0 18 C4.2 46.8 C26.2 C24.2 C58 C56 C4.0 15 22 C2 0 0 0 18 C4.2 44.8 C26.2 C24.2 C56 C54 C4.0 C5 22 10 6 0 0 18 C4.2 42.8 C26.2 C24.2 C54 C52 C4.0 C5 22 10 0 4 0 18 C4.2 40.8 C26.2 C24.2 data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 41 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 22. recommended egsm900/gsm850 agc data (2 of 2) (agc setpoint = C25.2 dbv = 55.0 mvrms) antenna input (dbm) i/q output (dbv) from to external front end losses (db) lna (db) mixer (db) lpf (db) vga1 (db) vga1 fine (db) aux (db) vga2 (db) internal inter- stage losses (db) total voltage gain (db) from to C52 C50 C4.0 C5 22 10 0 2 0 18 C4.2 38.8 C26.2 C24.2 C50 C48 C4.0 C5 22 10 0 0 0 18 C4.2 36.8 C26.2 C24.2 C48 C46 C4.0 C5 22 C2 6 4 0 18 C4.2 34.8 C26.2 C24.2 C46 C44 C4.0 C5 22 C2 6 2 0 18 C4.2 32.8 C26.2 C24.2 C44 C42 C4.0 C5 22 C2 6 0 0 18 C4.2 30.8 C26.2 C24.2 C42 C40 C4.0 C5 22 C2 0 4 0 18 C4.2 28.8 C26.2 C24.2 C40 C38 C4.0 C5 22 C2 0 2 0 18 C4.2 26.8 C26.2 C24.2 C38 C36 C4.0 C5 22 C2 0 0 0 18 C4.2 24.8 C26.2 C24.2 C36 C34 C4.0 C5 22 C2 0 4 0 12 C4.2 22.8 C26.2 C24.2 C34 C32 C4.0 C5 22 C2 0 2 0 12 C4.2 20.8 C26.2 C24.2 C32 C30 C4.0 C5 22 C2 0 0 0 12 C4.2 18.8 C26.2 C24.2 C30 C28 C4.0 C5 22 C2 0 4 0 6 C4.2 16.8 C26.2 C24.2 C28 C26 C4.0 C5 22 C2 0 2 0 6 C4.2 14.8 C26.2 C24.2 C26 C24 C4.0 C5 22 C2 0 0 0 6 C4.2 12.8 C26.2 C24.2 C24 C22 C4.0 C5 22 C2 0 4 0 0 C4.2 10.8 C26.2 C24.2 C22 C20 C4.0 C5 22 C2 0 2 0 0 C4.2 8.8 C26.2 C24.2 C20 C18 C4.0 C5 22 C2 0 0 0 0 C4.2 6.8 C26.2 C24.2 C18 C16 C4.0 C5 22 C2 0 0 0 0 C4.2 6.8 C24.2 C22.2 C16 C14 C4.0 C5 22 C2 0 0 0 0 C4.2 6.8 C22.2 C20.2 data sheet i cx74063-34/-35/-36 42 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 23. recommended dcs1800 agc data (1 of 2) (agc setpoint = C24.2 dbv = 61.7 mvrms) antenna input (dbm) i/q output (dbv) from to external front end losses (db) lna (db) mixer (db) lpf (db) vga1 (db) vga1 fine (db) aux (db) vga2 (db) internal inter- stage losses (db) total voltage gain (db) from to C110 C108 C4.2 15 40 10 24 0 0 18 C5.0 97.8 C25.2 C23.2 C108 C106 C4.2 15 40 10 18 4 0 18 C5.0 95.8 C25.2 C23.2 C106 C104 C4.2 15 40 10 18 2 0 18 C5.0 93.8 C25.2 C23.2 C104 C102 C4.2 15 40 10 18 0 0 18 C5.0 91.8 C25.2 C23.2 C102 C100 C4.2 15 40 10 12 4 0 18 C5.0 89.8 C25.2 C23.2 C100 C98 C4.2 15 40 10 12 2 0 18 C5.0 87.8 C25.2 C23.2 C98 C96 C4.2 15 40 10 12 0 0 18 C5.0 85.8 C25.2 C23.2 C96 C94 C4.2 15 40 10 6 4 0 18 C5.0 83.8 C25.2 C23.2 C94 C92 C4.2 15 40 10 6 2 0 18 C5.0 81.8 C25.2 C23.2 C92 C90 C4.2 15 40 10 6 0 0 18 C5.0 79.8 C25.2 C23.2 C90 C88 C4.2 15 40 10 0 4 0 18 C5.0 77.8 C25.2 C23.2 C88 C86 C4.2 15 40 10 0 2 0 18 C5.0 75.8 C25.2 C23.2 C86 C84 C4.2 15 40 10 0 0 0 18 C5.0 73.8 C25.2 C23.2 C84 C82 C4.2 15 40 C2 6 4 0 18 C5.0 71.8 C25.2 C23.2 C82 C80 C4.2 15 40 C2 6 2 0 18 C5.0 69.8 C25.2 C23.2 C80 C78 C4.2 15 40 C2 6 0 0 18 C5.0 67.8 C25.2 C23.2 C78 C76 C4.2 15 40 C2 0 4 0 18 C5.0 65.8 C25.2 C23.2 C76 C74 C4.2 15 40 C2 0 2 0 18 C5.0 63.8 C25.2 C23.2 C74 C72 C4.2 15 40 C2 0 0 0 18 C5.0 61.8 C25.2 C23.2 C72 C70 C4.2 15 22 10 0 4 0 18 C5.0 59.8 C25.2 C23.2 C70 C68 C4.2 15 22 10 0 2 0 18 C5.0 57.8 C25.2 C23.2 C68 C66 C4.2 15 22 10 0 0 0 18 C5.0 55.8 C25.2 C23.2 C66 C64 C4.2 15 22 10 6 4 0 18 C5.0 53.8 C25.2 C23.2 C64 C62 C4.2 15 22 C2 6 2 0 18 C5.0 51.8 C25.2 C23.2 C62 C60 C4.2 15 22 C2 6 0 0 18 C5.0 49.8 C25.2 C23.2 C60 C58 C4.2 15 22 C2 0 4 0 18 C5.0 47.8 C25.2 C23.2 C58 C56 C4.2 15 22 C2 0 2 0 18 C5.0 45.8 C25.2 C23.2 C56 C54 C4.2 15 22 C2 0 0 0 18 C5.0 43.8 C25.2 C23.2 C54 C52 C4.2 C7 22 10 6 2 0 18 C5.0 41.8 C25.2 C23.2 C52 C50 C4.2 C7 22 10 6 0 0 18 C5.0 39.8 C25.2 C23.2 data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 43 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 23. recommended dcs1800 agc data (2 of 2) (agc setpoint = C24.2 dbv = 61.7 mvrms) antenna input (dbm) i/q output (dbv) from to external front end losses (db) lna (db) mixer (db) lpf (db) vga1 (db) vga1 fine (db) aux (db) vga2 (db) internal inter- stage losses (db) total voltage gain (db) from to C50 C48 C4.2 C7 22 10 0 4 0 18 C5.0 37.8 C25.2 C23.2 C48 C46 C4.2 C7 22 10 0 2 0 18 C5.0 35.8 C25.2 C23.2 C46 C44 C4.2 C7 22 10 0 0 0 18 C5.0 33.8 C25.2 C23.2 C44 C42 C4.2 C7 22 C2 6 4 0 18 C5.0 31.8 C25.2 C23.2 C42 C40 C4.2 C7 22 C2 6 2 0 18 C5.0 29.8 C25.2 C23.2 C40 C38 C4.2 C7 22 C2 6 0 0 18 C5.0 27.8 C25.2 C23.2 C38 C36 C4.2 C7 22 C2 0 4 0 18 C5.0 25.8 C25.2 C23.2 C36 C34 C4.2 C7 22 C2 0 2 0 18 C5.0 23.8 C25.2 C23.2 C34 C32 C4.2 C7 22 C2 0 0 0 18 C5.0 21.8 C25.2 C23.2 C32 C30 C4.2 C7 22 C2 0 4 0 12 C5.0 19.8 C25.2 C23.2 C30 C28 C4.2 C7 22 C2 0 2 0 12 C5.0 17.8 C25.2 C23.2 C28 C26 C4.2 -7 22 C2 0 0 0 12 C5.0 15.8 C25.2 C23.2 C26 C24 C4.2 -7 22 C2 0 4 0 6 C5.0 13.8 C25.2 C23.2 C24 C22 C4.2 -7 22 C2 0 2 0 6 C5.0 11.8 C25.2 C23.2 C22 C20 C4.2 -7 22 C2 0 0 0 6 C5.0 9.8 C25.2 C23.2 C20 C18 C4.2 -7 22 C2 0 4 0 0 C5.0 7.8 C25.2 C23.2 C18 C16 C4.2 -7 22 C2 0 2 0 0 C5.0 5.8 C25.2 C23.2 C16 C14 C4.2 -7 22 C2 0 0 0 0 C5.0 5.8 C23.2 C21.2 data sheet i cx74063-34/-35/-36 44 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 24. recommended pcs1900 agc data (1 of 2) (agc setpoint = C25.4 dbv = 53.7 mvrms) antenna input (dbm) i/q output (dbv) from to external front end losses (db) lna (db) mixer (db) lpf (db) vga1 (db) vga1 fine (db) aux (db) vga2 (db) internal inter- stage losses (db) total voltage gain (db) from to C110 C108 C4.2 15 40 10 24 0 0 18 C6.2 96.6 C26.4 C24.4 C108 C106 C4.2 15 40 10 18 4 0 18 C6.2 94.6 C26.4 C24.4 C106 C104 C4.2 15 40 10 18 2 0 18 C6.2 92.6 C26.4 C24.4 C104 C102 C4.2 15 40 10 18 0 0 18 C6.2 90.6 C26.4 C24.4 C102 C100 C4.2 15 40 10 12 4 0 18 C6.2 88.6 C26.4 C24.4 C100 C98 C4.2 15 40 10 12 2 0 18 C6.2 86.6 C26.4 C24.4 C98 C96 C4.2 15 40 10 12 0 0 18 C6.2 84.6 C26.4 C24.4 C96 C94 C4.2 15 40 10 6 4 0 18 C6.2 82.6 C26.4 C24.4 C94 C92 C4.2 15 40 10 6 2 0 18 C6.2 80.6 C26.4 C24.4 C92 C90 C4.2 15 40 10 6 0 0 18 C6.2 78.6 C26.4 C24.4 C90 C88 C4.2 15 40 10 0 4 0 18 C6.2 76.6 C26.4 C24.4 C88 C86 C4.2 15 40 10 0 2 0 18 C6.2 74.6 C26.4 C24.4 C86 C84 C4.2 15 40 10 0 0 0 18 C6.2 72.6 C26.4 C24.4 C84 C82 C4.2 15 40 C2 6 4 0 18 C6.2 70.6 C26.4 C24.4 C82 C80 C4.2 15 40 C2 6 2 0 18 C6.2 68.6 C26.4 C24.4 C80 C78 C4.2 15 40 C2 6 0 0 18 C6.2 66.6 C26.4 C24.4 C78 C76 C4.2 15 40 C2 0 4 0 18 C6.2 64.6 C26.4 C24.4 C76 C74 C4.2 15 40 C2 0 2 0 18 C6.2 62.6 C26.4 C24.4 C74 C72 C4.2 15 40 C2 0 0 0 18 C6.2 60.6 C26.4 C24.4 C72 C70 C4.2 15 22 10 0 4 0 18 C6.2 58.6 C26.4 C24.4 C70 C68 C4.2 15 22 10 0 2 0 18 C6.2 56.6 C26.4 C24.4 C68 C66 C4.2 15 22 10 0 0 0 18 C6.2 54.6 C26.4 C24.4 C66 C64 C4.2 15 22 C2 6 4 0 18 C6.2 52.6 C26.4 C24.4 C64 C62 C4.2 15 22 C2 6 2 0 18 C6.2 50.6 C26.4 C24.4 C62 C60 C4.2 15 22 C2 6 0 0 18 C6.2 48.6 C26.4 C24.4 C60 C58 C4.2 15 22 C2 0 4 0 18 C6.2 46.6 C26.4 C24.4 C58 C56 C4.2 15 22 C2 0 2 0 18 C6.2 44.6 C26.4 C24.4 C56 C54 C4.2 15 22 C2 0 0 0 18 C6.2 42.6 C26.4 C24.4 C54 C52 C4.2 C5 22 10 6 0 0 18 C6.2 40.6 C26.4 C24.4 C52 C50 C4.2 C5 22 10 0 4 0 18 C6.2 38.6 C26.4 C24.4 data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 45 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 24. recommended pcs1900 agc data (2 of 2) (agc setpoint = C25.4 dbv = 53.7 mvrms) antenna input (dbm) i/q output (dbv) from to external front end losses (db) lna (db) mixer (db) lpf (db) vga1 (db) vga1 fine (db) aux (db) vga2 (db) internal inter- stage losses (db) total voltage gain (db) from to C50 C48 C4.2 C5 22 10 0 2 0 18 C6.2 36.6 C26.4 C24.4 C48 C46 C4.2 C5 22 10 0 0 0 18 C6.2 34.6 C26.4 C24.4 C46 C44 C4.2 C5 22 C2 6 4 0 18 C6.2 32.6 C26.4 C24.4 C44 C42 C4.2 C5 22 C2 6 2 0 18 C6.2 30.6 C26.4 C24.4 C42 C40 C4.2 C5 22 C2 6 0 0 18 C6.2 28.6 C26.4 C24.4 C40 C38 C4.2 C5 22 C2 0 4 0 18 C6.2 26.6 C26.4 C24.4 C38 C36 C4.2 C5 22 C2 0 2 0 18 C6.2 24.6 C26.4 C24.4 C36 C34 C4.2 C5 22 C2 0 0 0 18 C6.2 22.6 C26.4 C24.4 C34 C32 C4.2 C5 22 C2 0 4 0 12 C6.2 20.6 C26.4 C24.4 C32 C30 C4.2 C5 22 C2 0 2 0 12 C6.2 18.6 C26.4 C24.4 C30 C28 C4.2 C5 22 C2 0 0 0 12 C6.2 16.6 C26.4 C24.4 C28 C26 C4.2 C5 22 C2 0 4 0 6 C6.2 14.6 C26.4 C24.4 C26 C24 C4.2 C5 22 C2 0 2 0 6 C6.2 12.6 C26.4 C24.4 C24 C22 C4.2 C5 22 C2 0 0 0 6 C6.2 10.6 C26.4 C24.4 C22 C20 C4.2 C5 22 C2 0 4 0 0 C6.2 8.6 C26.4 C24.4 C20 C18 C4.2 C5 22 C2 0 2 0 0 C6.2 6.6 C26.4 C24.4 C18 C16 C4.2 C5 22 C2 0 0 0 0 C6.2 4.6 C26.4 C24.4 C16 C14 C4.2 C5 22 C2 0 0 0 0 C6.2 4.6 C24.4 C22.4 101514d 10_071101 figure 12. typical baseband frequency response data sheet i cx74063-34/-35/-36 46 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c 101514d 11_071101 sec figure 13. typical differential delay response table 25. egsm900/gsm850 lna s11 (normalized to 50 ? ) frequency (mhz) s11 869.0 0.386 C 0.632j 878.1 0.438 C 0.630j 887.2 0.454 C 0.629j 896.3 0.420 C 0.639j 905.4 0.403 C 0.642j 914.5 0.398 C 0.646j 923.6 0.371 C 0.653j 932.7 0.376 C 0.653j 941.8 0.379 C 0.657j 950.9 0.343 C 0.664j 960.0 0.350 C 0.664j data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 47 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 26. dcs1800 lna s11 (normalized to 50 ? ) frequency (mhz) s11 1805.0 0.0205 C 0.649j 1812.5 0.205 C 0.689j 1820.0 0.275 C 0.704j 1827.5 0.299 C 0.710j 1835.0 0.319 C 0.713j 1842.5 0.326 C 0.718j 1850.0 0.316 C 0.722j 1857.5 0.306 C 0.722j 1865.0 0.307 C 0.722j 1872.5 0.300 C 0.724j 1880.0 0.287 C 0.724j table 27. pcs1900 lna s11 (normalized to 50 ? ) frequency (mhz) s11 1930 0.237 C 0.583j 1936 0.362 C 0.595j 1942 0.432 C 0.591j 1948 0.472 C 0.589j 1954 0.489 C 0.591j 1960 0.488 C 0.597j 1966 0.483 C 0.600j 1972 0.485 C 0.600j 1978 0.484 C 0.600j 1984 0.475 C 0.603j 1990 0.465 C 0.605j data sheet i cx74063-34/-35/-36 48 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 28. typical egsm and gsm850 band noise figure vs. gain data gain nf gain nf gain nf gain nf gain nf gain nf 100.8 3.17 84.8 3.38 68.8 7.60 52.8 22.50 36.8 39.71 20.8 43.56 98.8 3.17 82.8 3.48 66.8 8.39 50.8 23.76 34.8 41.11 18.8 45.01 96.8 3.17 80.8 3.59 64.8 11.80 48.8 24.92 32.8 42.46 16.8 46.39 94.8 3.18 78.8 3.73 62.8 12.77 46.8 30.21 30.8 43.73 14.8 45.89 92.8 3.20 76.8 4.90 60.8 13.71 44.8 31.29 28.8 44.89 12.8 47.58 90.8 3.22 74.8 5.44 58.8 18.43 42.8 32.37 26.8 42.70 10.8 49.25 88.8 3.26 72.8 6.08 56.8 19.79 40.8 33.39 24.8 44.02 86.8 3.31 70.8 6.82 54.8 21.16 38.8 38.32 22.8 45.24 101514f 15_111201 noise figure (db) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0 20 40 60 80 100 120 rx voltage gain (db) figure 14. typical egsm and gsm850 band noise figure vs. voltage gain curve (cx74063-3x only, no front end loss) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 49 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 29. typical egsm and gsm850 band dynamic range data (includes 4.0 db front end loss) input noise floor p1db gain input noise floor p1db gain input noise floor p1db gain C109.0 C113.0 C78.6 97.8 C77.0 C108.2 C52.4 65.8 C45.0 C78.6 C21.2 33.8 C107.0 C113.0 C76.6 95.8 C75.0 C107.1 C52.0 63.8 C43.0 C74.5 C18.1 31.8 C105.0 C113.0 C74.6 93.8 C73.0 C106.0 C51.8 61.8 C41.0 C72.9 C17.7 29.8 C103.0 C113.0 C72.6 91.8 C71.0 C102.9 C43.4 59.8 C39.0 C71.4 C17.4 27.8 C101.0 C113.0 C70.6 89.8 C69.0 C101.6 C42.5 57.8 C37.0 C69.8 C17.2 25.8 C99.0 C113.0 C68.7 87.8 C67.0 C100.4 C41.9 55.8 C35.0 C68.3 C17.0 23.8 C97.0 C112.9 C66.9 85.8 C65.0 C96.4 C36.9 53.8 C33.0 C66.9 C17.0 21.8 C95.0 C112.9 C65.2 83.8 C63.0 C94.9 C35.9 51.8 C31.0 C66.9 C16.9 19.8 C93.0 C112.8 C63.7 81.8 C61.0 C93.4 C35.2 49.8 C29.0 C65.2 C16.9 17.8 C91.0 C112.7 C62.4 79.8 C59.0 C91.8 C34.6 47.8 C27.0 C63.4 C16.9 15.8 C89.0 C112.5 C61.4 77.8 C57.0 C90.3 C34.3 45.8 C25.0 C62.3 C16.8 13.8 C87.0 C112.3 C60.5 75.8 C55.0 C88.9 C34.0 43.8 C23.0 C60.3 C16.8 11.8 C85.0 C112.1 C59.9 73.8 C53.0 C83.8 C24.3 41.8 C21.0 C58.4 C16.8 9.8 C83.0 C110.8 C54.8 71.8 C51.0 C82.6 C23.2 39.8 C19.0 C56.7 C16.8 7.8 C81.0 C110.0 C53.8 69.8 C49.0 C81.3 C22.3 37.8 C17.0 C54.7 C16.8 5.8 C79.0 C109.2 C53.0 67.8 C47.0 C79.9 C21.7 35.8 C15.0 C52.7 C16.8 3.8 dbm -80.00 -60.00 -40.00 -20.00 -10.00 -120.00 -100.00 p1db input noise floor 101514f 16_111901 -60.0 -40.0 -20.0 0.0 antenna input (dbm) -120.0 -100.0 -80.0 + 4.0 db front end loss figure 15. typical egsm and gsm850 band dynamic range vs. antenna input curve data sheet i cx74063-34/-35/-36 50 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 30. typical dcs1800 band noise figure vs. gain data gain nf gain nf gain nf gain nf gain nf gain nf 100 3.7 84 3.9 68 8.3 52 23.3 36 41.1 20 48.0 98 3.7 82 4.0 66 9.1 50 24.6 34 42.5 18 46.4 96 3.7 80 4.1 64 12.6 48 25.7 32 43.9 16 47.8 94 3.7 78 4.3 62 13.6 46 32.0 30 45.3 14 49.2 92 3.7 76 5.5 60 14.5 44 33.0 28 46.5 12 48.7 90 3.7 74 6.1 58 19.2 42 34.1 26 47.7 10 50.4 88 3.8 72 6.7 56 20.6 40 35.2 24 45.5 86 3.8 70 7.5 54 22.0 38 36.2 22 46.8 101514f 17_111201 noise figure (db) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0 20 40 60 80 100 120 rx voltage gain (db) figure 16. typical dcs1800 band noise figure vs. voltage gain curve (cx74063-3x only; no front end loss) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 51 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 31. typical dcs1800 band dynamic range data (includes 4.2 db front end loss) input noise floor p1db gain input noise floor p1db gain input noise floor p1db gain C109.0 C113.0 C78.6 97.8 C77.0 C108.2 C52.4 65.8 C45.0 C78.6 C21.2 33.8 C107.0 C113.0 C76.6 95.8 C75.0 C107.1 C52.0 63.8 C43.0 C74.5 C18.1 31.8 C105.0 C113.0 C74.6 93.8 C73.0 C106.0 C51.8 61.8 C41.0 C72.9 C17.7 29.8 C103.0 C113.0 C72.6 91.8 C71.0 C102.9 C43.4 59.8 C39.0 C71.4 C17.4 27.8 C101.0 C113.0 C70.6 89.8 C69.0 C101.6 C42.5 57.8 C37.0 C69.8 C17.2 25.8 C99.0 C113.0 C68.7 87.8 C67.0 C100.4 C41.9 55.8 C35.0 C68.3 C17.0 23.8 C97.0 C112.9 C66.9 85.8 C65.0 C96.4 C36.9 53.8 C33.0 C66.9 C17.0 21.8 C95.0 C112.9 C65.2 83.8 C63.0 C94.9 C35.9 51.8 C31.0 C66.9 C16.9 19.8 C93.0 C112.8 C63.7 81.8 C61.0 C93.4 C35.2 49.8 C29.0 C65.2 C16.9 17.8 C91.0 C112.7 C62.4 79.8 C59.0 C91.8 C34.6 47.8 C27.0 C63.4 C16.9 15.8 C89.0 C112.5 C61.4 77.8 C57.0 C90.3 C34.3 45.8 C25.0 C62.3 C16.8 13.8 C87.0 C112.3 C60.5 75.8 C55.0 C88.9 C34.0 43.8 C23.0 C60.3 C16.8 11.8 C85.0 C112.1 C59.9 73.8 C53.0 C83.8 C24.3 41.8 C21.0 C58.4 C16.8 9.8 C83.0 C110.8 C54.8 71.8 C51.0 C82.6 C23.2 39.8 C19.0 C56.7 C16.8 7.8 C81.0 C110.0 C53.8 69.8 C49.0 C81.3 C22.3 37.8 C17.0 C54.7 C16.8 5.8 C79.0 C109.2 C53.0 67.8 C47.0 C79.9 C21.7 35.8 C15.0 C52.7 C16.8 3.8 dbm -80.00 -60.00 -40.00 -20.00 -10.00 -120.00 -100.00 p1db noise floor input 101514f 18_111201 -60.0 -40.0 -20.0 0.0 antenna input (dbm) -120.0 -100.0 -80.0 + 4.2 db front end loss figure 17. typical dcs1800 band dynamic range vs. antenna input curve data sheet i cx74063-34/-35/-36 52 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c table 32. typical pcs1900 band noise figure vs. gain data gain nf gain nf gain nf gain nf gain nf gain nf 98.8 4.2 82.8 4.5 66.8 9.3 50.8 24.5 34.8 42.3 18.8 49.2 96.8 4.2 80.8 4.6 64.8 10.1 48.8 25.8 32.8 43.7 16.8 47.6 94.8 4.2 78.8 4.7 62.8 13.7 46.8 26.9 30.8 45.1 14.8 49.0 92.8 4.2 76.8 4.9 60.8 14.7 44.8 33.2 28.8 46.5 12.8 50.4 90.8 4.2 74.8 6.3 58.8 15.6 42.8 34.2 26.8 47.7 10.8 49.9 88.8 4.3 72.8 6.9 56.8 20.4 40.8 35.3 24.8 48.9 8.8 51.6 86.8 4.3 70.8 7.6 54.8 21.8 38.8 36.4 22.8 46.7 6.8 53.3 84.8 4.4 68.8 8.4 52.8 23.1 36.8 37.4 20.8 48.0 101514f 19_111901 0 20 40 60 80 100 120 rx voltage gain (db) noise figure (db) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 figure 18. typical pcs1900 band noise figure vs. voltage gain curve (cx74063-3x only; no front end loss) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 53 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 table 33. typical pcs1900 band dynamic range data (includes 4.2 db front end loss) input noise floor p1db gain input noise floor p1db gain input noise floor p1db gain C109.0 C112.5 C77.4 96.6 C77.0 C107.4 C51.2 64.6 C45.0 C77.7 C20.3 32.6 C107.0 C112.5 C75.4 94.6 C75.0 C106.3 C50.8 62.6 C43.0 C73.5 C17.6 30.6 C105.0 C112.5 C73.4 92.6 C73.0 C105.2 C50.6 60.6 C41.0 C72.0 C17.2 28.6 C103.0 C112.5 C71.4 90.6 C71.0 C102.0 C42.2 58.6 C39.0 C70.4 C17.0 26.6 C101.0 C112.5 C69.4 88.6 C69.0 C100.7 C41.3 56.6 C37.0 C68.9 C16.8 24.6 C99.0 C112.5 C67.5 86.6 C67.0 C99.5 C40.7 54.6 C35.0 C67.4 C16.7 22.6 C97.0 C112.4 C65.7 84.6 C65.0 C95.4 C35.7 52.6 C33.0 C66.0 C16.6 20.6 C95.0 C112.4 C64.0 82.6 C63.0 C93.9 C34.7 50.6 C31.0 C66.3 C16.6 18.6 C93.0 C112.3 C62.5 80.6 C61.0 C92.4 C34.0 48.6 C29.0 C64.6 C16.5 16.6 C91.0 C112.1 C61.2 78.6 C59.0 C90.9 C33.4 46.6 C27.0 C62.9 C16.5 14.6 C 89.0 C112.0 C60.2 76.6 C57.0 C89.4 C33.1 44.6 C25.0 C61.8 C16.5 12.6 C87.0 C111.8 C59.3 74.6 C55.0 C88.0 C32.8 42.6 C23.0 C59.9 C16.5 10.6 C85.0 C111.5 C58.7 72.6 C53.0 C82.8 C23.3 40.6 C21.0 C58.0 C16.5 8.6 C83.0 C110.0 C53.6 70.6 C51.0 C81.6 C22.2 38.6 C19.0 C56.3 C16.5 6.6 C81.0 C109.3 C52.6 68.6 C49.0 C 80.3 C21.4 36.6 C17.0 C54.3 C16.5 4.6 C79.0 C108.4 C51.8 66.6 C47.0 C79.0 C20.8 34.6 C15.0 C52.4 C16.5 2.6 101514f 20_111901 dbm -80.00 -60.00 -40.00 -20.00 -10.00 -120.00 -100.00 -60.0 -40.0 -20.0 0.0 antenna input (dbm) -120.0 -100.0 -80.0 +4.2 db front end loss p1db noise floor input figure 19. typical pcs1900 band dynamic range vs. antenna input curve data sheet i cx74063-34/-35/-36 54 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c 50 45 40 35 30 25 20 15 10 5 0 1100 1200 1300 1400 1500 1600 vco frequency (mhz) 101514f 21_111901 control sensitivity (mhz/v) specification limits typical performance figure 20. typical control sensitivity, uhf vco 35 30 25 20 15 10 5 0 750 800 850 900 950 vco frequency (mhz) 101514f 22_111901 control sensitivity (mhz/v) specification limits typical performance figure 21. typical control sensitivity, low band tx vco 30 25 20 15 10 5 0 1600 1700 1800 1900 2000 vco frequency (mhz) 101514f 23_111901 control sensitivity (mhz/v) specification limits typical performance 1650 1750 1850 1950 figure 22. typical control sensitivity, high band tx vco data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 55 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 transmitter data s094 center 836.4 mh z ?70 ?80 ?90 ?95 ?60 ?50 ?40 ?30 ?20 ?10 5 0 span 1 mhz 100 khz/ relative power (db) [t1] = 2.61 dbm 836.400 00000 mhz [t1] = ?67.91 db ?400.000 00000 khz [t1] = ?67.69 db 400.000 00000 khz rbw 30 khz rf att 20 db vbw 30 khz mixer ?20 dbm swt 5 ms unit dbm 1 1 1 2 1 2 figure 23. typical gsm850 band output spectrum s095 center 902.4 mh z ?70 ?80 ?90 ?95 ?60 ?50 ?40 ?30 ?20 ?10 5 0 span 1 mhz 100 khz/ relative power (db) [t1] = 3.02 dbm 902.400 00000 mhz [t1] = ?68.37 db ?400.000 00000 khz [t1] = ?87.71 db 400.000 00000 khz rbw 30 khz rf att 20 db vbw 30 khz mixer ?20 dbm swt 5 ms unit dbm 1 1 1 2 1 2 figure 24. typical egsm band output spectrum data sheet i cx74063-34/-35/-36 56 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c s096 center 1.7478 gh z ?70 ?80 ?90 ?95 ?60 ?50 ?40 ?30 ?20 ?10 5 0 span 1 mhz 100 khz/ relative power (db) [t1] = 0.0 9 dbm 1.7478000 0 ghz [t1] = ?67.66 db ?400.000 00000 khz [t1] = ?67.32 db 400.000 00000 khz rbw 30 khz rf att 20 db vbw 30 khz mixer ?20 dbm swt 5 ms unit dbm 1 1 2 1 1 2 figure 25. typical dcs band output spectrum s097 center 1.88 ghz ?70 ?80 ?90 ?95 ?60 ?50 ?40 ?30 ?20 ?10 5 0 span 1 mhz 100 khz/ relative power (db) [t1] = 0.75 dbm 1.88000 000 ghz [t1] = ?64.79 db ?400.000 00000 khz [t1] = ?64.58 db 400.000 00000 khz rbw 30 khz rf att 20 db vbw 30 khz mixer ?20 dbm swt 5 ms unit dbm 1 1 2 1 1 2 figure 26. typical pcs band output spectrum data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 57 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 cx74063-34/-35/-36 multi-band gsm transceiver c3 1 nf v_rf rxin rxip rxqn rxqp vlogic vsyn c5 680 pf le clk data sxena data 1 rxena txena pco vcxo_en txcpo gsm rx input lna1800in pdet lna1900in nc c25 1 nf v_rf v_rf v_rf dcs rx input in out ground 1 3 4 6 f1 gsm saw 2 5 pdetvcc vcc1 7 8 9 10 txinp lna900in gndlna900 11 12 13 14 15 nc r7 39 k ? c16 470 pf c15 470 pf c22 100 nf pcs rx input txqn txqp txin txip v_rf v_rf to baseband 2 in out ground 1 3 4 6 f3 dcs saw 5 in out ground 1 3 4 6 f2 pcs saw 5 2 capqn capqp capin capip vcc2 txifn txifp txqn txqp txin txip bbvapc pavapc c24 1.0 pf c23 0.5 pf c21 1.2 pf l2 6.8 nh r1 5.6 k ? r2 2 k ? c7 8.2 nf 2 3 4 rxena txena vcxo_en 5 6 r6 680 ? c17 39 pf r3 270 ? c8 39 pf l6 220 nh xtal tune 22 pf 82 nh pavapc bbvapc c18 3.9 nf c28 1.8 pf rf detector to antenna rf out coupler pa rf in pavapc l4 10 nh c12 1 nf dcs/pcs tx to pa gsm tx to pa uhftu ne uhfbyp vccuhf vcc3 rxqn rxqp rxin rxip vcc4 vcctxvco txvco tune tx1800/tx1900 tx900 56 55 54 53 52 51 50 49 48 47 46 45 44 16 17 18 19 20 21 22 23 24 25 26 27 28 l5 1.5 nh r5 390 ? r4 510 ? r8 50 ? l1 10 nh l3 3.3 nh c1 100 nf c2 220 pf + c4 1 f c27 0.1 f c26 1 nf xtal tune clk le vddbb 43 42 41 40 39 38 sxena vccfn_cp uhfcpo gndfn 37 36 35 34 33 32 31 30 29 xtal vccf vccd gndd xtal buf lpfadj vsyn c11 1 nf c14 0.1f c13 0.1 f v_rf crystal 1000 pf c1331 figure 27. typical cx74063- 3x application circuit data sheet i cx74063-34/-35/-36 58 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c 8.00 0.10 0.38 0.08 r2.70 re f 0.30 0.05 0.50 ref 8.00 0.10 1.00 0.10 top view side view bottom view pin 1 c1339 all dimensions are in millimeters pin 1 figure 28. 56-pin rflga package dimens ion drawing (cx74063-34 and CX74063-35 options) 8.00 0.10 0.38 0.08 0.30 0.05 0.50 ref 8.00 0.10 1.00 0.10 top view side view bottom view pin 1 s288 all dimensions are in millimeters pin 1 r0.25 (12x) 0.56 ref r2.70 ref figure 29. 56-pin rflga package di mension drawing (cx74063-36 option) data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 59 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 2.00 0.10 0.318 .02 1.73 0.10 8.40 0.10 8 o max 8.40 0.10 12.00 0.10 1.50 0.25 4.00 0.10 1.50 0.10 7 o max 1.75 0.10 7.50 0.10 16.00 + 0.30/?0.10 s109a notes: 1. carrier tape material: black conductive polycarbonate or polystyrene 2. cover tape material: transparent conductive psa 3. cover tape size: 13.3 mm width 4. all measurements are in millimeters pin #1 indicator ab a b b a figure 30. 56-pin rflga tape and r eel dimensions (cx74063-34/36 options) 2.00 0.10 0.318 .02 1.73 0.10 8.40 0.10 8 o max 8.40 0.10 12.00 0.10 1.50 0.25 4.00 0.10 1.50 0.10 7 o max 1.75 0.10 7.50 0.10 16.00 + 0.30/?0.10 s109 notes: 1. carrier tape material: black conductive polycarbonate or polystyrene 2. cover tape material: transparent conductive psa 3. cover tape size: 13.3 mm width 4. all measurements are in millimeters pin #1 indicator ab a b b a figure 31. 56-pin rflga tape and r eel dimensions (CX74063-35 option) data sheet i cx74063-34/-35/-36 60 skyworks solutions, inc., proprietary and confidential november 25, 2003 [781] 376-3000 i fax [781] 376-3100 i sales@ skyworksinc.com i www.skyworksinc.com 103116c note 1 : the pin 1 id is a triangle o r circle. note 2 : brand line 1 . the part numb er format is cxpp ppp-dd. the cx prefix is the company ide ntifier. p = five-digit part number, d = dash number (for example, -34, - 35). the cx prefix may no t appear on small d evices. the part n umber m ay be followed by a "p" to indicate a prototype dev ice. ( note 3 ) brand line 2 . lot number and l ot split identifier. t he lot number fo rmat = 6 alphanu meric characters followed by a 1- o r 2-digit lot split identifier separated b y a decimal point. the format is a123 45.2 or a12345.21 . ( note 3 ) brand line 3 . date code and c ountry of origin. t he date code shou ld be the same for the entire lot numb er and lot split identifier. the first two digit s of the date cod e are the current accountin g calendar year. the last two digits are the c urrent accounting calen dar week. the format is y yww (for examp le, 0225). the co untry of origin is th e full name of the c ountry where assembly is completed (for example, mexico). the country of origin ma y be abbreviated (f or example, usa or cn) if backside marking is not po ssible because of size res trictions. ( note 3 ) a vendor-specified logo may appea r below brand line 3 (for example, ar m). note 3 : as long as the device form, fit, and fu nction remain the sa me, the data in bra nd lines 1-3 may change . for example, the lot number and lot s plit identi fier may change; th e date code and country of origin may change if sk yworks selects a second assembly source. mark pin 1 id ( note 1 ) cx74063-dd k16102.5 0325 usa brand lin e 1: part number ( note 2 ) brand lin e 2: lot number a nd lot split identifie r ( note 2 ) brand line 3: date code, c ountry of origin ( note 2 ) c1403c figure 32. typical case markings data sheet i cx74063-34/-35/-36 skyworks solutions, inc., pr oprietary and confidential 61 103116c [781] 376-3000 i fax [781] 376-3100 i sales@skywor ksinc.com i www.skyworksinc.com november 25, 2003 ordering information model name manufactu ring part number product revision cx74063: msl3/240, circular ground pad msl3/260, circular ground pad msl3/260, four-quadrant ground pad cx74063-34 CX74063-35 cx74063-36 ? 2003 skyworks solutions, inc. all rights reserved. information in this document is pr ovided in connection with skyworks solutions, inc. ("skyworks") products. these materials are provided by skyworks as a service to its customers and may be used for informational purposes only. skyw orks assumes no responsibility fo r errors or omissions in these materials. skyworks may make changes to its products, specifications and product descriptions at any time, without no tice. skyworks makes no commitment to update th e information and shall have no responsibility whatsoever for conf licts, incompatibilities, or other difficulties ar ising from future changes to its products a nd product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. exce pt as may be provided in skyworks terms and conditions of sale for such products, skyworks assumes no liability whatsoever. these materials are provided "as is" without warranty of any kind, either express or implied, relating to sale and/or use of sk yworks? products including warranties relating to fi tness for a particular purpose, merchanta bility, performance, quality or non-infrin gement of any patent, copyright or other intellectual pr operty right. skyworks further does not warra nt the accuracy or completeness of the i nformation, text, graphics or other items contained within these materials. skyworks shall not be liable for any special, indirect, inciden tal, or consequential damages, including without limitation, lost revenues or lost profit s that may result from the use of these materi als. skyworks? products are not intended for use in medical, lifesav ing or life-sustaining applicatio ns. skyworks customers using o r selling skyworks? products for use in such applications do so at their own risk and agree to fully indemnify skyworks for any damages resulting from such improper us e or sale. the following are trademarks of skyworks solutions, inc.: skywor ks?, the skyworks symbol, single package radio?, spr?, and b reakthrough simplicity?. product names or services listed in this pub lication are for identification purposes only , and may be trademarks of third parti es. third-party brands and names are the property of their respective owners. gsm?, global system for mobile communication s?, and the gsm logo are trademarks of the gsm association. rflga? is a trademark of conexant systems, inc. additional information, posted at www.skywor ksinc.com, is incorporated by reference. general information skyworks solutions, inc. 20 sylvan rd. woburn, ma 01801 www.skyworksinc.com |
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